1 CMPE511 Term Paper Presentation Afşin ÖZPINAR EE Phd ARM Soft Microprocessor Architectures

2 Overview What is ARM? The History of ARM Why ARM? ARM Overview and Market Partners Processor Cores and Development ARM Product Family and Comparision Key Features of the ARM ARM Architecture ARM11TDMI Multiprocessor Structure AMBA Bus Structure ARM Instruction set ARM Based Products

3 What is ARM? ARM stands for Advanced RISC Machine A Reduced Instruction Set Computer (RISC) developed by a company called Acorn Computers Ltd. ARM is the world leader company in IP offerings consist of a wide range of microprocessor cores, architectural extensions, development tools, peripheral IP and SoC solutions. All of these solutions are supported by ARM and a global network of design and engineering Partners

4 The History of ARM ARM was established in November 1990 as Advanced RISC Machines Ltd., a UK-based joint venture between Apple Computer, Acorn Computer Group and VLSI Technology. Acorn, developer of the worlds first commercial single- chip RISC processor, and Apple, intent on advancing the use of RISC technology in its own systems, chartered ARM with creating a new microprocessor standard. With the introduction of its first embedded RISC core, the ARM6 family of processors, in 1991, ARM signed VLSI as its initial licensee.

5 Why ARM? ARM core-based microprocessors are used in industry commonly because: Tools of Choice - ARM has the widest range of hardware and software tools support any 32 bit architecture Ease of Access – There are more than 10 leading microcontroller suppliers providing ARM based MCUs Flexibility in System Design – Through a wide range of functionality and power, parts running 1 MHz to 1 GHz with architectural performance enhancements for media and Java Low Cost of Silicon – Processors and other products making efficient use of silicon while designing any kind of chips

6 ARM Overview ARMs 16/32-bit RISC microprocessors, data engines, peripherals, software and tools, combined with the companys broad Partner community, provide a total system solution that offers a fast, reliable path to market for leading electronics companies ARMs RISC technology addresses todays design challenges, providing many advantages over competing architectures: Not only do ARM cores offer an unrivalled combination of advanced logic, robust functionality, energy efficiency and low cost, but their simpler designs enable easy integration. In addition, their superior code densities allow for reduced memory and consequently, lower system costs

7 Market ARM designs the technology that lies at the heart of advanced digital products:

8 ARM : General As the industrys leading provider of 32-bit embedded RISC microprocessors,with almost 75% of the market ARM offers a wide range of processor cores,all using a common underlying architecture, to deliver high performance with low power consumption at minimal cost The ARM architectures performance range extends to more than 1 GHz ARMs strength lies in the fact that it has over 100 partners throughout the world

9 ARM and the Partners ARM is the number one semiconductor IP supplier in the world ARM Powered® microprocessors are pervasive in the electronic products we use, driving key functions in a variety of applications in the market ARM licenses its IP to a network of Partners, which includes some of the worlds leading semiconductor and system companies. These Partners utilise ARMs low -cost, power efficient core designs to create and manufacture microprocessors, peripherals and SoC solutions

10 Some of the Partners Alcatel, Analog Devices, Atmel, Epson, Ericsson, Fujitsu, IBM, Infineon, Intel, Kawasaki, Mitsubishi, Motorola, National Semiconductor, NEC, Panasonic, Philips, Samsung, Sharp, Sony, ST Microelectronics, Texas Instruments, Toshiba, Yamaha Operating Systems Partners: Mentor Graphics, Microsoft, Sun Microsystems,

11 Processor Cores ARM offers a wide range of processor cores & solutions based on a common architecture, that deliver high performance together with low power consumption and system cost: Embedded Cores Application Cores Secure Cores OptimoDE Data Engine

12 ARM Product Family There are currently seven main product families: ARM7 ARM9 ARM9E ARM10 ARM11 SecurCore Cortex Families Further implementations available from ARMs partners (such as Intel® XScale technology and StrongARM® products) with available performance over 1 GHz

13 Architecture Revisions time version ARMv5 ARMv V4 StrongARM ® ARM926EJ-S XScale TM ARM102xE ARM1026EJ-S ARM9x6E ARM92xT ARM1136JF-S ARM7TDMI-S ARM720T XScale is a trademark of Intel Corporation Future SC100 SC200

14 Thumb ® DSP Jazelle ® Media Performance Architectures ARM v4T ARM v5TE ARM v5TEJ ARM v6 Architecturev4Tv5TEv5TEJv6Architecturev4Tv5TEv5TEJv6 Feature Set ARM7 and ARM9 Family ARM10 Family ARM11 Family

15 ARM Family Comparision

16 Performance Changes The ARM architecture is now the industrys leading 32-bit embedded RISC microprocessor solution All ARM processors share this architecture, ensuring that developers gain on software development as they move to higher performance processors

17 Key Features of The Architecture(1) Some of the key features of the ARM architecture: Thumb® : ARM processors are native 32-bit designs, but also incorporate the 16-bit Thumb instruction set which enables software to be coded as shorter 16-bit instructions. This provides typical memory savings of up to 35 while retaining all the benefits of a 32-bit system SIMD Technology: The ARM SIMD (Single Instruction Multiple Data) media extensions increase the processing capability of ARM solutions DSP : A set of arithmetic instructions for DSP applications. The addition of the DSP instruction set offers 16-bit and 32-bit arithmetic capabilities Jazelle : An extension to enable direct execution of Java byte- codes in hardware Media : 2-4x performance increase for audio and video processing

18 Key Features of The Architecture(2) ARM TrustZone : Provides a secure foundation for systems running open Operating Systems (OS), to ensure that data downloaded or run on the device remains secure The ARM Intelligent Energy Manager (IEM): Implements advanced algorithms to optimally balance processor workload and energy consumption. The Intelligent Energy Manager technology works with the operating system dynamically predict the required future CPU performance level for the applications running on the mobile phone The ARM OptimoDE : An extremely configurable VLIW-styled data engine architecture, targeted at intensive non-stop data processing ARM NEON : Presents an extensive set of new instructions for future ARM processors that is a 64/128-bit hybrid SIMD architecture

19 The ARM11 microarchitecture is the first implementation of the ARMv6 instruction set architecture, and forms the basis of a new family of ARM11 cores Key Benefits The ARM11 microarchitecture represents a major step in system performance with target performance for the first cores in the MHz to over 1GHz. Processor implementations based on the ARM11 microarchitecture will achieve less than 0.4mW/MHz at 1.2V in a 0.13µm process technology. The ARM11 microarchitecture has been developed both for synthesizable and semicustom hard macrocell implementations. Since, primarily, the cores will be used within a system on a chip (SoC) context, enabling implementation through synthesis allows developers to easily integrate the design. To better facilitate synthesis, ARM11 cores have a synthesis-friendly pipeline structure designed to work with commercially available synthesis tools The ARM11 microarchitecture – through the ARM v6 architecture, also benefits software developers. It includes a large set of media processing instructions to accelerate audio and video applications Some Details on ARM11 Family

20 ARM Microprocessor Core

21 ARM11 Pipeline ARM11 Microarchitecture – Pipelining Differing from preceding ARM cores the ARM11 consists of 8 stages An 8-stage pipeline allows 8 different processing stages to be carried out simultaneously Highly-pipelined structures can impair efficiency by introducing excessive delays, or latency, into the system. Forwarding: Long pipelines mean that execution of some instructions may be delayed, because they depend on the results of previous instructions the ARM11 pipeline avoids these delays by extensive use of forwarding within the pipeline. Predecting: The ARM11 also has a fetaure of branch predecting

22 ARM11 Pipeline

23 Example ARM System

24 The ARM MPCore The ARM MPCore TM synthesizable multiprocessor is based on the ARM11 TM microarchitecture Can be configured to contain between one and four processors delivering up to 2600 Dhrystone MIPS of performance The new ARM multiprocessor solution delivers greater performance at lower frequencies than comparable single processor solutions The MPCore enables system designers to view the core as a single uniprocessor, simplifying development and reducing time-to-market. The MPCore multiprocessor supports up to four-way cache coherent symmetric multiprocessing (SMP), up to four-way asymmetric multiprocessing (AMP), or any combination of both. The MPCore also supports the partitioning of processors to support traditional asymmetric multiprocessing (AMP) providing software compatibility for existing applications and increased throughput when multiple applications are run in parallel

25 MPCore Features Highly configurable Flexibility of total available performance from implementations using between 1 and 4 processors Sizing of both data and instruction cache between 16K and 64K bytes across each processor Either dual or single 64-bit AMBA 3.0 AXI system bus connection allowing rapid and flexibility during SoC design Optional integrated vector floating point (VFP) unit Efficient processing Rich ARMv6 architecture-based multiprocessor-capable instruction set architecture Support for ARM Thumb ® instruction set,ARM Jazelle ® technology, ARM DSP extensions SIMD (single instruction, multiple data) media processing extensions delivering up to 2x performance for video processing Advanced Operating System (AOS) extensions providing architectural enhancements that improve performance of a multiprocessor capable OS.

26 MPCore Features Energy Efficient Low power system design allowing gate level shutdown of unused resources Support for ARM Intelligent Energy Management (IEM) Various levels of individual processor shutdown providing up to 85% energy saving on both dynamic and static energy usage High Performance Memory 16-64k independent data and instruction cache per processor with full data coherence Ability for data to be copied between each processors cache permitting rapid data sharing without accesses to main memory Simple Design Integration Utilizes 64-bit AMBA AXI bus interconnect Software Support Environment

27 The ARM MPCore

28 AMBA Overview Standard for On-Chip Bus AMBA is an open standard, on-chip bus specification that details a strategy for the interconnection and management of functional blocks that makes up a System-on-Chip (SoC) It facilitates "right-first-time" development of embedded processors with one or more CPU/signal processors and multiple peripherals AMBA enhances a reusable design methodology by defining a common backbone for SoC modules AMBA Flexibility For the on-chip bus, flexibility is the key to reuse by enabling developers to select the optimal architecture to efficiently meet the performance requirements of a wide variety of systems. AMBA enables the SoC designer to select the optimal combination of bus frequency (to match the peripherals) and number of channels (to achieve the bandwidth), using the AMBA Multi-layer architecture

29 AMBA Overview AMBA Compatibility The AMBA interface standards ensure that peripherals can be reused with confidence in a multitude of systems AMBA compliance provides the mechanism to ensure reuse of peripherals between systems AMBA Support AMBA has been widely adopted throughout the industry and, as a consequence, there is support for the development of AMBA bus- based systems from a growing number of companies

30 The ARM Instruction Set Architecture The ARM architecture provides support for the 32-bit ARM and 16-bit Thumb ® Instruction Set Architectures along with architecture extensions to provide support for Java acceleration (Jazelle) and security (TrustZone) technologies ARMv4 ARMv4 can be considered a 32-bit ISA operating in a 32-bit address space. ARMv4T The ARMv4T architecture added the 16-bit Thumb instruction set which enabled compilers to generate more compact code while retaining all the benefits of a 32-bit system. ARMv5TE Thumb architecture, along with ARM Enhanced DSP instruction set extensions to the ARM ISA. ARMv5TEJ The Jazelle extension to support Java acceleration technology.

31 The ARM Instruction Set Architecture ARMv6 The ARMv6 architecture includes media instructions to support Single Instruction Multiple Data(SIMD) software execution. The SIMD extensions are optimized for a broad range of software applications including video and audio codecs, where the extensions increase performance by up to four times. NEON TM Media Acceleration Technology ARM NEON technology is designed to address the demands of next generation high-performance, media intense, low power mobile handheld devices. NEON technology is a 64/128-bit hybrid SIMD architecture Vector Floating Point (VFP) Vector Floating Point (VFP) coprocessor support is an architecture option. The VFP architecture supports single and double precision floating point arithmetic

32 Some of ARM Based Products Atmel AT91SC25672RC - Secure MCU AT91 Series - Micro Controllers Motorola DragonBall TM / i.MX, i.MXL, i.MX1, i.MX21 NEC High performance / low risk SoC Design Philips LPC2000 series microcontrollers Samsung S3F/C - ARM core-based MCUs Texas Instruments TMS320DSC25 - Digital Signal Processor ST Microelectronics Mobile Multimedia Processor Platform

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