전자의료시스템 및 실습 System Configuration/Interrupt 구 환 경희대학교 전자정보대학 동서의료공학과

Architecture Summary 2007 Summer Seminar

DSP Initialization Decision - Clock frequency - Wait state of external ROM, RAM, I/O - Enable peripheral module by supplying clock 2007 Summer Seminar

Configuration Registers 2007 Summer Seminar

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Reset 2007 Summer Seminar

Wait-State Generation 2007 Summer Seminar

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Clock Generation 2007 Summer Seminar

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External Memory Interface C240x PLL Clock Module XTAL1/CLKIN WDCLK 1/512 Prescaler Watchdog crystal FIn PLL Clock Module 3-bit PLL Select XTAL OSC CPU Core Memory CAN Event Manager SCI SPI External Memory Interface XTAL2 CLKOUT ADCCLK Prescaler ADC CLK PS2 CLK PS1 CLK PS0 Clock Frequency 1 4 x FIn 2 x FIn 1.33 x FIn 1 x FIn 0.8 x FIn 0.66 x FIn 0.57 x FIn 0.5 x Fin (default) 2007 Summer Seminar

Watch-dog Timer Clock 2007 Summer Seminar

Watchdog Timer Resets the C240x if the CPU crashes Watchdog must be serviced (or disabled) within ~3.28ms after reset(40 MHz device) This translates into 131,072 instructions! - Watchdog counter runs independent of CPU - If counter overflows, reset is triggered - CPU must write correct data key sequence to reset the counter before overflow 2007 Summer Seminar

Watchdog Timer Module 6 – bit Free – Running Counter /64 111 /32 110 WDPS /16 101 WDCLK /8 100 WDCR.2.0 /4 011 /2 010 WDCR.6 System Reset 001 CLR WDDIS 000 WDCNTR.7-0 WDFLAG 8 – bit Watchdog Counter CLR One-Cycle Delay WDCR.7 System Reset Request WDKEY.7-0 WDCR.5-3 WDCHK 2-0 Watchdog Reset Key Register 55 + AA Detector Good Key 3 Bad Key Bad WDCR Key 3 1 2007 Summer Seminar

Watchdog Period Selection WDPS Bits FRC rollover C240x timeout Period @ 40 MHz 00x: 010: 011: 100: 101: 110: 111: 1 2 4 8 16 32 64 3.28 ms 6.55 ms 13.11 ms 26.21 ms 52.43 ms 104.86 ms 209.72 ms WDPS set to 000 after any CPU reset Watchdog starts counting immediately after reset is released 2007 Summer Seminar

Watchdog Timer Control Register WDCR @ 7029h WD Flag Bit Gets set when the WD causes a reset Writing a 1 clears this bit Writing a 0 has no effect 15-8 7 6 5 4 3 2 1 reserved WDFLAG WDDIS WDCHK2 WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0 Logic check Bit Write as 101 or reset Immediately triggered WD Prescale Selection Bits Watchdog Disable Bit (Function only if WD OVERRIDE Bit in SCSR2 is equal to 1) 2007 Summer Seminar

Resetting the Watchdog WDKEY @ 7025h 15-8 7 6 5 4 3 2 1 reserved D7 D6 D5 D4 D3 D2 D1 D0 Allowable write values: - 55h – counter enabled for reset followed by an AAh - AAh – counter set to zero if reset enabled Writing any other value immediately triggers a CPU reset Watchdog should not be serviced solely in an ISR - If main code crashes, but interrupt continues to execute, the watchdog will not catch the crash - Could put the 55h WDKEY in the main code, and the AAh WDKEY in an ISR; this catches main code crashes and also ISR crashes 2007 Summer Seminar

WDKEY Write Results Sequential Step Value Written to WDKEY Result 1 2 3 4 5 6 7 8 9 10 11 AAh 55h 23h No action NO action WD counter enabled for reset on next AAh write WD counter is reset CPU reset triggered due to improper write value 2007 Summer Seminar

Low-Power Modes 2007 Summer Seminar

Interrupt Description ※ 폴링(Polling) 방식 - 어떤 작업을 수행 중이라도 다른 작업이 필요하다면 필요하다는 신 호를 받은 후 다른 작업을 마치고 나서 예전에 하던 작업의 나머지 부분을 계속하는 방식 ※ 폴링(Polling) 방식 - 어떤 신호가 발생하기만을 계속하여 기다리면서 다른 일은 하지 못 하고 있다가 해당 신호가 발생하면 해당 작업을 마친 후에야 비로서 그 다음 작업을 수행하는 형식 2007 Summer Seminar

Maskable Interrupt Timeline Valid External signal Individual flag bit set Individual interrupt enabled? Core interrupt flag bit set Core interrupt enabled? Global interrupt switch enabled? interrupt hardware sequence Branch to ISR (interrupt vectors) H A R D W E S O F T W A R E 9. Interrupt Service Routine 2007 Summer Seminar

Interrupt Requests 2007 Summer Seminar

Individual Flag and Mask Bits Interrupt management Individual Flag and Mask Bits To core Interrupt INT1 XINT1 flag polarity enable Arbitrator XINT2 flag polarity enable ADCINT flag enable 2007 Summer Seminar

Conceptual Core Overview Interrupt management Conceptual Core Overview (INTM) “Global Switch” (IFR) “Latch” Core Interrupt (IMR) “Switch” C240x core INT1 1 INT2 INT3 1 A valid signal on a specific interrupt line causes the latch to display a “1” in the appropriate bit. If the individual and Global switches are turned on, the interrupt reaches the core. 2007 Summer Seminar

Interrupt Registers 2007 Summer Seminar

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2007 Summer Seminar