ECE 667 Synthesis and Verification of Digital Circuits Boolean SAT Slides adapted from students presentation, Girish Paladugu (ECE 667 Spring 2011) ECE 667

Overview Introduction: motivation, brief history Conjunctive Normal Form (CNF) DPLL Method for solving SAT problems Backtrack search algorithm Applications Conclusion ECE 667 - Synthesis & Verification - SAT 2 ECE 667 2

INTRODUCTION SAT: Given a Boolean formula (propositional logic formula) find a variable assignment such that the formula evaluates to 1 (SAT), or prove that no such assignment exists (unSAT). For n variables, there are 2n possible truth assignments to be checked. F = (a + b)(a’ + b’ + c) a b c 1 The first established NP-Complete problem. S. A. Cook, The complexity of theorem proving procedures, Proceedings, Third Annual ACM Symp. on the Theory of Computing,1971, 151-158 ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Conjunctive Normal Form Conjunctive Normal Form (CNF): A conjunctive normal form (CNF) formula ϕ on n binary variables x1, …, xn is the conjunction of m clauses ω1, …, ωm. Literal: it is the occurrence of a variable x or its complement x’. Clause: It is the disjunction of one or more literals. Example CNF formula is satisfiable if each clause is satisfiable( evaluate to true) else it is unsatisfiable. j = ( a + c ) ( b + c ) (¬a + ¬b + ¬c ) ECE 667 - Synthesis & Verification - SAT 4

Applications Core computational engine for major applications EDA Testing and Verification Logic synthesis FPGA routing Path delay analysis Test Pattern Generation Artificial Intelligence Knowledge base deduction Automatic theorem proving ECE 667 - Synthesis & Verification - SAT

Equivalence Checking CA z = 1 ? CB If z = 1 is unsatisfiable, the two circuits are equivalent ! ECE 667 - Synthesis & Verification - SAT

Automatic Test Pattern Generation (ATPG) x1 x2 x3 x4 x5 x6 x7 x8 x9 s-a-1 x4 x1 x2 x3 x5 x6 x7 x8 x9 = 0 CG z = 1 ? x4 x1 x2 x3 x5 x6 x7 x8 x9 = 1 CF x4 x1 x3 x5 x6 x7 x8 x9 ECE 667 - Synthesis & Verification - SAT

Development of SAT: a Brief History 2005 MiniSAT ~15k var Main contributions in SAT research: 1960: Davis and Putnam – resolution based - dealing with ~10 variables 1962: Davis, Logemann and Loveland – DFS-based – dealing with ~10 variables Basic framework for many modern SAT solvers 1986: R. E. Bryant – BDD-based – dealing with ~100 variables 1996: Silva and Sakallah – GRASP (conflict-driven learning and non-chronological backtracking) – dealing with ~1k variables 2001: Malik et al. – Efficient BCP and decision making – dealing with ~10k vars ECE 667 - Synthesis & Verification - SAT Adopted from S. Malik, Princeton University ECE 667

Deriving CNF for Logic Gate b d jd = [d = ¬(a b)] = ¬[d Å ¬(a b)] jd = [d = ¬(a b )][¬d = a b] = ¬[¬(a b)¬d + a b d] = [d = ¬a + ¬b][¬d = a b] = ¬[¬a ¬d + ¬b ¬d + a b d] = (¬a ® d)(¬b ® d)(a b ® ¬d) = (a + d)(b + d)(¬a + ¬b + ¬d) = (a + d)(b + d)(¬a + ¬b + ¬d) Show alternate method (characteristic function) Point to the difference between satisfying the CNF formula solving for the output value ECE 667 - Synthesis & Verification - SAT

CNF Formulas for simple gates ECE 667 - Synthesis & Verification - SAT 10

Circuit - CNF conversion ECE 667 - Synthesis & Verification - SAT 11 ECE 667 11

DLL Algorithm Davis, Logemann and Loveland M. Davis, G. Logemann and D. Loveland, “A Machine Program for Theorem-Proving", Communications of ACM, Vol. 5, No. 7, pp. 394-397, 1962 Also known as DPLL for historical reasons (P = Putman) It is basically an intelligent Depth First Search (DFS) Binary Covering Problem (BCP) Basic framework for many modern SAT solvers ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Example Single gate (^a+^b+ c)(a+^c)(b+^c) Circuit in AIG form: network of connected AND gates (^1+2+4)(1+^4)(^2+^4) (^2+^3+5)(2+^5)(3+^5) (2+^3+6)(^2+^6)(3+^6) (^4+^5+7)(4+^7)(5+^7) (5+6+8)(^5+^8)(^6+^8) (7+8+9)(^7+^9)(^8+^9) (^9) 1 6 2 5 8 7 3 4 9 Note: Nodes 1,2,3: PI Nodes 4,5,6,7,8,9: AND gates Justify to “0” ECE 667 - Synthesis & Verification - SAT ECE 667

Circuit Satisfiability d e g f h a b c d e g f h? a b c d e g f h? a b c d e g f h? a b c d e g f h? j = h [d=¬(ab)] [e=¬(b+c)] [f=¬d] [g=d+e] [h=fg] = h (a + d)(b + d)(¬a + ¬b + ¬d) (¬b + ¬e)(¬c + ¬e)(b + c + e) (¬d + ¬f)(d + f) (¬d + g)(¬e + g)(d + e + ¬g) (f + ¬h)(g + ¬h)(¬f + ¬g + h) = h (a + d)(b + d)(¬a + ¬b + ¬d) (¬b + ¬e)(¬c + ¬e)(b + c + e) (¬d + ¬f)(d + f) (¬d + g)(¬e + g)(d + e + ¬g) (f + ¬h)(g + ¬h)(¬f + ¬g + h) = h (a + d)(b + d)(¬a + ¬b + ¬d) (¬b + ¬e)(¬c + ¬e)(b + c + e) (¬d + ¬f)(d + f) (¬d + g)(¬e + g)(d + e + ¬g) (f + ¬h)(g + ¬h)(¬f + ¬g + h) = h (a + d)(b + d)(¬a + ¬b + ¬d) (¬b + ¬e)(¬c + ¬e)(b + c + e) (¬d + ¬f)(d + f) (¬d + g)(¬e + g)(d + e + ¬g) (f + ¬h)(g + ¬h)(¬f + ¬g + h) = h (a + d)(b + d)(¬a + ¬b + ¬d) (¬b + ¬e)(¬c + ¬e)(b + c + e) (¬d + ¬f)(d + f) (¬d + g)(¬e + g)(d + e + ¬g) (f + ¬h)(g + ¬h)(¬f + ¬g + h) ECE 667 - Synthesis & Verification - SAT ECE 667

Conjunctive Normal Form (CNF) Clause j = ( a + c ) ( b + c ) (¬a + ¬b + ¬c ) Negative Literal Positive Literal ECE 667 - Synthesis & Verification - SAT ECE 667

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) (a + c’ + d) (a + c’ + d’) (b’ + c’ + d) (a’ + b + c’) (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) (a + c’ + d) (a + c’ + d’) (b’ + c’ + d) (a’ + b + c’) (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d)  Decision (a + c + d’) (a + c’ + d) (a + c’ + d’) (b’ + c’ + d) (a’ + b + c’) (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) b (a + c’ + d)  Decision (a + c’ + d’) (b’ + c’ + d) (a’ + b + c’) (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) b (a + c’ + d) (a + c’ + d’) (b’ + c’ + d) c (a’ + b + c’)  Decision (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) b (a + c’ + d) (a + c’ + d’) (b’ + c’ + d) c (a’ + b + c’) (a’ + b’ + c) (a + c + d) a=0 d=1 Conflict! Implication Graph c=0 d=0 (a + c + d’) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) b (a + c’ + d) (a + c’ + d’) (b’ + c’ + d) c (a’ + b + c’) (a’ + b’ + c) (a + c + d) a=0 d=1 Conflict! Implication Graph c=0 d=0 (a + c + d’) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) b (a + c’ + d) (a + c’ + d’) (b’ + c’ + d) c  Backtrack (a’ + b + c’) (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) b (a + c’ + d) (a + c’ + d’) (b’ + c’ + d) c (a’ + b + c’) 1  Forced Decision (a’ + b’ + c) (a + c’ + d) a=0 d=1 Conflict! c=1 d=0 (a + c’ + d’) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) b (a + c’ + d) (a + c’ + d’) (b’ + c’ + d) c  Backtrack (a’ + b + c’) 1 (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) b (a + c’ + d) 1  Forced Decision (a + c’ + d’) (b’ + c’ + d) c (a’ + b + c’) 1 (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) b (a + c’ + d) 1 (a + c’ + d’) (b’ + c’ + d) c c (a’ + b + c’) 1  Decision (a’ + b’ + c) (a + c + d) a=0 d=1 Conflict! c=0 d=0 (a + c + d’) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) b (a + c’ + d) 1 (a + c’ + d’) (b’ + c’ + d) c c  Backtrack (a’ + b + c’) 1 (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) b (a + c’ + d) 1 (a + c’ + d’) (b’ + c’ + d) c c (a’ + b + c’) 1 1  Forced Decision (a’ + b’ + c) (a + c’ + d) a=0 d=1 Conflict! c=1 d=0 (a + c’ + d’) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS  Backtrack (a’ + b + c) (a + c + d) (a + c + d’) b (a + c’ + d) 1 (a + c’ + d’) (b’ + c’ + d) c c (a’ + b + c’) 1 1 (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) 1  Forced Decision (a + c + d) (a + c + d’) b (a + c’ + d) 1 (a + c’ + d’) (b’ + c’ + d) c c (a’ + b + c’) 1 1 (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) 1 (a + c + d) (a + c + d’) b b (a + c’ + d) 1  Decision (a + c’ + d’) (b’ + c’ + d) c c (a’ + b + c’) 1 1 (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) 1 (a + c + d) (a + c + d’) b b (a + c’ + d) 1 (a + c’ + d’) (b’ + c’ + d) c c (a’ + b + c’) 1 1 (a’ + b’ + c) (a’ + b + c) a=1 c=1 Conflict! b=0 c=0 (a’ + b + c’) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) 1 (a + c + d) (a + c + d’) b b  Backtrack (a + c’ + d) 1 (a + c’ + d’) (b’ + c’ + d) c c (a’ + b + c’) 1 1 (a’ + b’ + c) ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) 1 (a + c + d) (a + c + d’) b b (a + c’ + d) 1 1  Forced Decision (a + c’ + d’) (b’ + c’ + d) c c (a’ + b + c’) 1 1 (a’ + b’ + c) (a’ + b’ + c) a=1 c=1 b=1 ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) 1 (a + c + d) (a + c + d’) b b (a + c’ + d) 1 1 (a + c’ + d’) (b’ + c’ + d) c c (a’ + b + c’) 1 1 (a’ + b’ + c) (a’ + b’ + c) (b’ + c’ + d) a=1 c=1 d=1 b=1 ECE 667 - Synthesis & Verification - SAT Slide adapted From ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Basic DLL Procedure - DFS (a’ + b + c) 1 (a + c + d) (a + c + d’) b b (a + c’ + d) 1 1 (a + c’ + d’) (b’ + c’ + d) c c  SAT (a’ + b + c’) 1 1 (a’ + b’ + c) (a’ + b’ + c) (b’ + c’ + d) a=1 c=1 d=1 b=1 ECE 667 - Synthesis & Verification - SAT Slide adapted from ‘The Quest for Efficient Boolean Satisfiability Solvers’ – Sharad Malik

Backtrack Search Algorithm The algorithm conducts a search through the space of the possible assignments to the problem instance variables The search is improved by Resolution Clause recording Recursive learning Backtrack search has proven useful for solving instances of SAT from EDA applications, in particular for applications where the objective is to prove unsatisfiability. ECE 667 - Synthesis & Verification - SAT 38 ECE 667 38

Backtrack Search SAT Algorithm ECE 667 - Synthesis & Verification - SAT 39

Methods in the Backtrack SAT Algorithm Decide( ): Identify the necessary assignments Deduce( ): Returns a conflict indication whenever a clause becomes unSAT Diagnose( ): Analyzes the conflict and returns a decision level to which the search process is required to backtrack Erase( ): Clears implied assignments that results from each assignment selection Preprocess( ): Preprocessing before running SAT algorithm. ECE 667 - Synthesis & Verification - SAT 40

Summary of SAT Techniques Techniques for Backtrack Search Formula simplification & clause inference Conflict analysis Clause/implicate recording Non-chronological backtracking Resolution Recursive learning Randomization & Restarts ECE 667 - Synthesis & Verification - SAT