Synthesis of sequential circuits

Slides:



Advertisements
Similar presentations
Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo.
Advertisements

Some Slides from: U.C. Berkeley, U.C. Berkeley, Alan Mishchenko, Alan Mishchenko, Mike Miller, Mike Miller, Gaetano Borriello Gaetano Borriello Introduction.
VIII - Working with Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 1 Finite state machine optimization State minimization  fewer.
CS 151 Digital Systems Design Lecture 25 State Reduction and Assignment.
Sequential Circuit Design
ECE 331 – Digital System Design State Reduction and State Assignment (Lecture #22) The slides included herein were taken from the materials accompanying.
ECE 331 – Digital System Design
Sequential Circuit Design. 2 State Optimization Equivalent States:  Two states are equivalent if, for each member of the set of inputs,  they give exactly.
ECE C03 Lecture 111 Lecture 11 Finite State Machine Optimization Hai Zhou ECE 303 Advanced Digital Design Spring 2002.
FSMs 1 Sequential logic implementation  Sequential circuits  primitive sequential elements  combinational logic  Models for representing sequential.
EDA (CS286.5b) Day 17 Sequential Logic Synthesis (FSM Optimization)
ECE C03 Lecture 131 Lecture 13 Finite State Machine Optimization Prith Banerjee ECE C03 Advanced Digital Design Spring 1998.
Sequential System Synthesis -- State Encoding. ENEE 6442 The State Encoding Problem > Goal: Given n states, assign a unique code (of length of at least.
1 COMP541 State Machines Montek Singh Feb 6, 2007.
Sequential Circuit Design
Spring 2002EECS150 - Lec0-intro Page 1 EECS150 - Digital Design Lecture 9 - Finite State Machines 1 February 19, 2002 John Wawrzynek.
Spring 2002EECS150 - Lec15-seq2 Page 1 EECS150 - Digital Design Lecture 15 - Sequential Circuits II (Finite State Machines revisited) March 14, 2002 John.
ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)
ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)
ENGIN112 L25: State Reduction and Assignment October 31, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 25 State Reduction and Assignment.
CSCI 3301 Transparency No. 9-1 Chapter #9: Finite State Machine Optimization Contemporary Logic Design.
IKI c-Synthesis of Sequential Logic Bobby Nazief Semester-I The materials on these slides are adopted from: Prof. Daniel Gajski’s transparency.
1 COMP541 State Machines Montek Singh Feb 8, 2012.
L10 – State Machine Design Topics. States Machine Design  Other topics on state machine design Equivalent sequential machines Incompletely specified.
1 COMP541 Finite State Machines - 1 Montek Singh Sep 22, 2014.
1 COMP541 Sequential Logic – 2: Finite State Machines Montek Singh Feb 29, 2016.
CS137: Electronic Design Automation
Capabilities, Minimization, and Transformation of Sequential Machines
Finite state machine optimization
Sequential Networks and Finite State Machines
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN
Figure 8.1. The general form of a sequential circuit.
Finite state machine optimization
ANALYSIS OF SEQUENTIAL CIRCUITS
Lecture 13 Derivation of State Graphs and Tables
Sequential logic design principles
Adapted by Dr. Adel Ammar
COMP541 Sequential Logic – 2: Finite State Machines
FINITE STATE MACHINES (FSMs)
Instructor: Alexander Stoytchev
Sequential circuit design
COE 561 Digital System Design & Synthesis Sequential Logic Synthesis
Instructor: Alexander Stoytchev
Sequential circuit design
Instructor: Alexander Stoytchev
Synthesis and Verification of Finite State Machines
CSE 370 – Winter Sequential Logic-2 - 1
Lecture 25 Logistics Last lecture Today HW8 posted today, due 12/5
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES
L10 – additional State Machine examples
Sequential circuit design
Implement FSM with fewest possible states • Least number of flip flops
CHAPTER 15 REDUCTION OF STATE TABLES STATE ASSIGNMENT
DESIGN OF SEQUENTIAL CIRCUITS
Synthesis and Verification of Finite State Machines
Lecture 25 Logistics Last lecture Today HW8 posted today, due 12/5
CSE 370 – Winter Sequential Logic-2 - 1
ECE 352 Digital System Fundamentals
Lecture 22 Logistics Last lecture Today
Guest Lecture by David Johnston
ECE 352 Digital System Fundamentals
EGR 2131 Unit 12 Synchronous Sequential Circuits
ECE 352 Digital System Fundamentals
Instructor: Alexander Stoytchev
ECE 352 Digital System Fundamentals
Announcements Assignment 7 due now or tommorrow Assignment 8 posted
Chapter5: Synchronous Sequential Logic – Part 3
CSE 370 – Winter Sequential Logic-2 - 1
Chapter 9 -- Simplification of Sequential Circuits
Presentation transcript:

Synthesis of sequential circuits Steps in synthesis of a sequential circuit Specify the FSM (state table or state diagram) Minimize the states State assignment/encoding Specification: PS x NS z S1 S3 1 S5 S2 S4 0/1 0/0 S3 S1 S4 1/1 1/1 0/0 0/1 0/1 1/0 1/1 S2 S5 1/1

State minimization (Completely specified FSM) Completely specified  no don’t cares Progressively refine a set of equivalence classes, j For the state machine on the previous slide 0 = all states in one class = {{S1, S2, S3, S4, S5}} 1: distinguished on the basis of output value 1 = {{S1,S2},{S3,S4},{S5}} 2: distinguished if NS for two states in a partition are in different partitions. Example: For x=1, NS for S3  {S1,S2}; NS for S4 {S5} 2 = {{S1,S2},{S3}{S4},{S5}} Continue finding j+1 given j in a similar way Stop when j+1 = j since this implies that k = j for all k > j In this example, 3 = 2 Final set of equivalence classes = {{S1,S2},{S3}{S4},{S5}}

State minimization (Completely specified FSM) – Contd. Final set of equivalence classes = {{S1,S2},{S3}{S4},{S5}} State table shown at right Complexity: Let ns = # states At most O(ns) iterations Each iteration is O(ns) Total complexity is O(ns2) A more clever implementation can achieve O(ns log ns) PS x NS z S1 S3 1 S5 S4

State minimization (Incompletely specified FSM) PS x NS z S1 S3 1 S5 d S2 S4 Idea of equivalence does not hold any more Equivalence involves Reflexivity (si <comp> si) Symmetry (si <comp> sj)  (sj <comp> si) Transitivity (si <comp> sj) and (sj <comp> sk)  (si <comp> sk) For the state table here, looking at compatibility only in terms of the output value (similar to constructing 1 for a completely specified FSM) s1 <comp> s2, s2 <comp> s3 but s1 is not compatible with s3 Need to work with compatibilities instead of equivalences

State minimization (Incompletely specified FSM) – Contd. Example: state table shown on previous slide List (possibly) compatible states and clearly incompatible states List conditions under which states could be compatible Compatible Incompatible {S1,S2} {S1,S3} {S1,S5}  {S3,S4} {S1,S4} {S2,S3}  {S1,S5} {S2,S5} {S2,S4}  {S3,S4} {S3,S5} {S3,S4}  {S2,S4}, {S1,S5} {S4,S5} {S1,S5} are compatible if {S3,S4} are compatible Now use list of incompatible states to iteratively strike out states from compatible set and move them to the incompatible set No such update possible here, although in general it may be possible Combine now as {S2,S3,S4}  {S1,S5} and {S1,S5}  {S3,S4}: consistent Result: combine {S2,S3,S4} into one state and {S1,S5} into another

State encoding Assign Boolean codes to states Two extremes One-hot encoding: n bits for n states, only one bit set to 1 Example: S1 = 1000, S2 = 0100, S3 = 0010, S4 = 0001 Large # of state bits (and hence FF’s), simple combinational logic due to extensive don’t care space Minimum-bit encoding: log2 n bits for n states Example: S1 = 00, S2 = 01, S3 = 10, S4 = 11 Small # of state bits, possibly more complex combinational logic More commonly used Can also be in between the extremes

State assignment heuristics “Fanout oriented” Same NS from two PS under a given input should be assigned neighboring codes Example: two inputs X1,X2 and one output Z Rationale: state table will include which implies that 0-01  fon(NS2), fon(NS1), fon(Z) 01/1 01 00 11 PS2 PS1 X1 X2 NS2 NS1 Z 1

State assignment heuristics – contd. “Fanin oriented” If a PS goes to two different NS’s, they should be assigned neighboring codes Example: two inputs X1,X2 and one output Z Rationale: state table will include which implies that 011-  fon(NS1), fon(Z) 01 10/1 11/1 10 11 PS2 PS1 X1 X2 NS2 NS1 Z 1

A simple state-assignment algorithm Considers fanin oriented case only and defines “attractions” Construct matrices ns x ns between states Entry (i,j) = # of transitions from i to j ns x noutputs between states and outputs Entry (i,j) = # output transitions with value 1 0/0 S1 1/1 1/1 0/0 1/0 0/0 S3 S2 NS1 NS2 NS3 PS1 1 PS2 PS3 Z PS1 1 PS2 PS3

State assignment algorithm Attraction metric between states Si and Sj = Nb PSi PSjT + zi zjT where Nb = # state bits, PSk = row k of state matrix zk = row k of output matrix Attraction12 = 2[110][101]T + [1][0] = 2 Attraction23 = 2[101][101]T + [0][1] = 4 Attraction13 = 2[110][101]T + [1][1] = 3 Build attraction graph Start with node with max sum of edge attractions and assign it an encoding (here, S3 is arbitrarily assigned 00) Assign encodings in order of attraction to neighbors to reduce Hamming distance (here, S2 = 01, S1 = 10) Repeat until all states are assigned codes (here, we are done) 10 S1 3 2 4 S3 S2 00 01