Lecture 4 Sums of Product Circuits Simplification

Slides:



Advertisements
Similar presentations
Techniques for Combinational Logic Optimization
Advertisements

Combinational Logic Circuits Chapter 2 Mano and Kime.
ECE 3110: Introduction to Digital Systems Simplifying Sum of Products using Karnaugh Maps.
Contemporary Logic Design Two-Level Logic © R.H. Katz Transparency No. 3-1 Chapter #2: Two-Level Combinational Logic Section 2.1, Logic Functions.
Example: Given a 4-bit input combination N=N 3 N 2 N 1 N 0, this function produces a 1 output for N=1,2,3,5,7,11,13, and 0 otherwise.  According to the.
Chapter 4 Logic Gates and Boolean Algebra. Introduction Logic gates are the actual physical implementations of the logical operators. These gates form.
CSCE 211: Digital Logic Design
EECC341 - Shaaban #1 Lec # 7 Winter Combinational Circuit Minimization Canonical sum and product logic expressions do not provide a circuit.
Simplifying Boolean Expressions Using K-Map Method
Chapter 2: Boolean Algebra and Logic Functions
Chapter 2 Combinational Systems And / Or / Not. TRIAD PRINCIPLE: Combinational is about And / Or / Not combinations As well as equivalent functions. It.
2 - 1 Chapter 2 Combinational Systems Chapter 2 Combinational Systems 2.1 The Design Process for Combinational Systems  Continuing Example(CE)
F = ∑m(1,4,5,6,7) F = A’B’C+ (AB’C’+AB’C) + (ABC’+ABC) Use X’ + X = 1.
ECE 2110: Introduction to Digital Systems PoS minimization Don’t care conditions.
Physics 343 Advanced Electronics Engineering 343 Digital Systems Electronics Courses.
Chapter 4 Combinational Logic Design Principles. Overview Objectives -Define combinational logic circuit -Analysis of logic circuits (to describe what.
Circuit Minimization. It is often uneconomical to realize a logic directly from the first logic expression that pops into your head. Canonical sum and.
PRASAD A. PAWASKAR SPN. NO DETE 2 SEMESTER lec1-11.
Chapter 2 Two- Level Combinational Logic. Chapter Overview Logic Functions and Switches Not, AND, OR, NAND, NOR, XOR, XNOR Gate Logic Laws and Theorems.
CHAPTER 3: PRINCIPLES OF COMBINATIONAL LOGIC
Lecture 4 Nand, Nor Gates, CS147 Circuit Minimization and
ENG241 Digital Design Week #2 Combinational Logic Circuits.
Chap 2. Combinational Logic Circuits
ES 244: Digital Logic Design Chapter 2 Chapter 2: Combinational Systems Adapted from Alan Marcovitz’s Introduction to Logic and Computer Design Uchechukwu.
ece Parity Used to check for errors Can be either ODD or EVEN Left most bit used as the indicator For EVEN, insert a 0 or a 1 so as to make the.
ECE 3110: Introduction to Digital Systems Chapter #4 Review.
CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic 4: Cost of Logic Circuits and Karnaugh Maps José Nelson Amaral.
Chapter 2 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Combinational Systems.
ECE DIGITAL LOGIC LECTURE 8: BOOLEAN FUNCTIONS Assistant Prof. Fareena Saqib Florida Institute of Technology Spring 2016, 02/11/2016.
Lecture 3 Boolean algebra Topics Error Correcting Codes Boolean algebra Combinational circuits Algebraic analysis, Truth tables, Logic Diagrams Sums-of-Products.
©2010 Cengage Learning SLIDES FOR CHAPTER 4 APPLICATIONS OF BOOLEAN ALGEBRA MINTERM AND MAXTERM EXPANSIONS Click the mouse to move to the next page. Use.
Mu.com.lec 9. Overview Gates, latches, memories and other logic components are used to design computer systems and their subsystems Good understanding.
CHAPTER 3 Simplification of Boolean Functions
CS2100 Computer Organisation
Logic Gates and Boolean Algebra
Chapter 2 Combinational Systems
Lecture 4 Nand, Nor Gates, CS147 Circuit Minimization and
Chapter 2: Boolean Algebra and Logic Functions
ECE 2110: Introduction to Digital Systems
Computer Organisation
ECE 20B, Winter 2003 Introduction to Electrical Engineering, II LECTURE NOTES #2 Instructor: Andrew B. Kahng (lecture)
ECE 3110: Introduction to Digital Systems
CHAPTER 2 Boolean Algebra
CHAPTER 2 Boolean Algebra This chapter in the book includes:
Boolean Algebra and Combinational Logic
Princess Sumaya University
Circuit analysis summary
ECE 2110: Introduction to Digital Systems
Lecture 3 Gunjeet Kaur Dronacharya Group of Institutions
Computer Architecture CST 250
ECE 331 – Digital System Design
EEL 3705 / 3705L Digital Logic Design
CSE 140 : Components and Design Techniques for Digital Systems
Boolean Algebra.
Lecture 3 Boolean algebra
Boolean Algebra.
Lecture 14: Boolean Algebra
ECE 331 – Digital System Design
Digital Logic & Design Dr. Waseem Ikram Lecture 13.
CSE 370 – Winter Combinational Logic - 1
Combinatorial Logic Circuit
Chapter 3 Gate-level Minimization.
MINTERMS and MAXTERMS Week 3
Overview Part 2 – Circuit Optimization
Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and NOT. These operations can.
Basic circuit analysis and design
Chapter 4 Combinational Logic Design Principles. Overview Objectives -Define combinational logic circuit -Analysis of logic circuits (to describe what.
Circuit Simplification and
ECE 331 – Digital System Design
Presentation transcript:

Lecture 4 Sums of Product Circuits Simplification CSCE 211 Digital Design Lecture 4 Sums of Product Circuits Simplification Topics Circuit Simplification Sums-of-Products September 3, 2015

Overview Last Time: Readings Chapter 2, New: Homework Boolean algebra Lec 2 slides: two’s complement overflow Lec 3 slides 1-23 Boolean algebra Combinational circuits Algebraic analysis, Truth tables, Logic Diagrams New: NAND and NOR gates Lec 3 slides: The rest of them; we just covered a few Karnaugh maps Sums-of-Products and Products-of-Sums Homework Chapter 2: 2f, 5c, 11c, Prove n variable Demorgan’s law via Induction (not the version done in class), 13.a,b,e

Pop Quiz What is the representation in 10 bit of the largest unsigned int? Value? What is the representation of the largest two’s complement number in 10 bits? If an IEEE 754 float has exponent 42 what is the exponent field?

Lecture 03 slides 23- Algebraic Simpl. Proof by Induction Universal Sets Universal Sets (cont) Combinational Circuit Analysis Switching Algebra Terminology Timing Analysis Circuit Simplification Sums-of Products Circuit Simplification Karnaugh Map Karnaugh Map Simplification Karnaugh Map Term. … … Prime Implicants Karnaugh Map Simp. Ex Example Four Variable Maps

Gates again! NAND Gate NOR Gate

Circuit Simplification Why would we want to simplify circuits? To minimize time delays To minimize costs To minimize area

Boolean Algebra Reformulated P1a. a + b = b + a P2a. a+(b+c) = (a+b)+c P3a. a + 0 = a P4a. 1 + a = 1 P5a. a + a’ = 1 P6a. a + a = a P7. (a’)’ = a P8a a(b+c) = ab + ac P9a. ab+ab’ = a P10a. a + a’b = a + b

Sums-of-Products What is the delay of sums-of-products circuit?

Continuing Examples (CE) CE1. A system with four inputs, A, B, C, and D, and one output, Z, such that Z=1 if three of the inputs are 1. CE2. A single light (that can be on or off) that can be controlled by any one of three switches. One switch is the master on/off switch. If it is off, the lights are off. When the master switch is on, a change in the position of one of the other switches (from up to down or from down to up) will cause the light to change state. CE3. A system to do 1 bit of binary addition. It has three inputs (the 2 bits to be added plus the carry from the next lower order bit) and produces two outputs, a sum bit and a carry to the next higher order position. CE4. A system that has as its input the code for a decimal digit, and produces as its output the signals to drive a seven-segment display, such as those on most digital watches and numeric displays. CE5. A system with nine inputs, representing two 4-bit binary numbers and a carry input, and one 5-bit output, representing the sum. (Each input number can range from 0 to 15; the input can range from 0 to 31.)

Procedure for implementing Combinational Circuits Step 1: Represent each of the inputs and output in binary. Step 1.5: If necessary, break the problem into smaller subproblems. Step 2: Formalize the design specification either in the form of a truth table or of an algebraic expression. Step 3: Simplify the description. Step 4: Implement the system with the available components, subject to the design objectives and constraints.

CE1. A system with four inputs, A, B, C, and D, and one output, Z, such that Z=1 if three of the inputs are 1.

CE2. A single light (that can be on or off) that can be controlled by any one of three switches. One switch is the master on/off switch. If it is off, the lights are off. When the master switch is on, a change in the position of one of the other switches (from up to down or from down to up) will cause the light to change state.

CE3. Full Adder CE3. A system to do 1 bit of binary addition. It has three inputs (the 2 bits to be added plus the carry from the next lower order bit) and produces two outputs, a sum bit and a carry to the next higher order position.

CE4. A system that has as its input the code for a decimal digit, and produces as its output the signals to drive a seven-segment display, such as those on most digital watches and numeric displays.

CE5. 4-bit binary adder A system with nine inputs, representing two 4-bit binary numbers and a carry input, and one 5-bit output, representing the sum. (Each input number can range from 0 to 15; the input can range from 0 to 31.)

Definitions A literal is the appearance of a variable or its complement. A product term is one or more literals connected by AND operators. A standard product term, also minterm is a product term that includes each variable of the problem, either uncomplemented or complemented. A sum of products expression (often abbreviated SOP) is one or more product terms connected by OR operators. A canonical sum or sum of standard product terms is just a sum of products expression where all of the terms are standard product terms.

A minimum sum of products expression is one of those SOP expressions for a function that has the fewest number of product terms. If there is more than one expression with the fewest number of terms, then minimum is defined as one or more of those expressions with the fewest number of literals. (1) x´yz´ + x´yz + xy´z´ + xy´z + xyz 5 terms, 15 literals (2) x´y + xy´ + xyz 3 terms, 7 literals (3) x´y + xy´ + xz 3 terms, 6 literals (4) x´y + xy´ + yz 3 terms, 6 literals

A sum term is one or more literals connected by OR operators. A standard sum term, also called a maxterm, is a sum term that includes each variable of the problem, either uncomplemented or complemented. A product of sums expression (POS) is one or more sum terms connected by AND operators. A canonical product or product of standard sum terms is just a product of sums expression where all of the terms are standard sum terms. SOP: x´y + xy´ + xyz POS: (x + y´)(x´ + y)(x´ + z´) Both: x´ + y + z or xyz´ Neither: x(w´ + yz) or z´ + wx´y + v(xz + w´)

For any two product terms where exactly one variable appears uncomplemented in one and complemented in the other, the consensus is defined as the product of the remaining literals. If no such variable exists or if more than one such variable exists, then the consensus us undefined. If we write one term as at1 and the second as a´t2 (where t1 and t2 represent product terms), then, if the consensus is defined. at1 ¢ a´t2 = t1t2 P13a. at1 + a´t2 + t1t2 = at1 + a´t2 P13b. (a + t1)(a + t2)(t1 + t2)= (a + t1)(a + t2)

G = DE´ + A´B´C + CD´E + ABC´E G = C´ (A´B´ + ABE) + DE´ + CD´E G = C´ (B´ + E)(B + A´) + DE´ + CD´E G = (C´ + D´ E)[C + (B´ + AE)(B + A´)] + DE´

Circuit Simplification Minterms – a product term in which every variable occurs once either complemented or uncomplemented X Y F minterm 1 X’ . Y’ X’ . Y X . Y’ X . Y Sum of minterms form: F(X,Y) = X’ . Y’ + X . Y’ + X . Y F(X,Y) = Σ(0, 2, 3) (sum of minterms m, with F(m)=1

Karnaugh Maps Tabular technique for simplifying circuits two variable maps three variable map XYZ XY X 1 1 00 01 11 10 Z Y 00 10 01 11 000 010 110 100 001 011 111 101 1 X XY 0 1 Y 1 00 01 11 10 Z 2 1 3 1 2 6 4 1 3 7 5

Karnaugh Map Simplification Simplify F(X,Y,Z) = Σ(0,2,6,4,7,5) XY 00 01 11 10 Z 1 1 Z F(X,Y,Z)= Minimize ? – here it will mean “fewer gates, fewer inputs”

Karnaugh Map Terminology F(X,Y,Z) = Σ(1,4,5,6,7) XY 00 01 11 10 Z 1 1 Z Implicant set - rectangular group of size 2i of adjacent containing ones (with wraparound adjacency) Each implicant set of size 2i corresponds to a product term in which i variables are true and the rest false Implicant Sets:

Karnaugh Map Terminology F(X,Y,Z) = XY 00 01 11 10 Z 1 Z Prime implicant – an implicant set that is as large as possible Implies – We say P implies F if everytime P(X1, X2, … Xn) is true then F (X1, X2, … Xn) is true also. If P(X1, X2, … Xn) is a prime implicant then P implies F

Karnaugh Map Terminology F(X,Y,Z) = XY 00 01 11 10 Z 1 1 Z Prime implicants – If P(X1, X2, … Xn) is a prime implicant then P implies F and if we delete any variable from P this does not imply F.

Karnaugh Map Simplification F(X,Y,Z) = XY 00 01 11 10 Z 1 Z F(X,Y,Z) =

Karnaugh Map Simplification F(X,Y,Z) = XY 00 01 10 11 Z 1 Z F(X,Y,Z) =

4 Variable Map Simplification F(W,X,Y,Z) = X WX 00 01 11 10 YZ 0000 0100 1100 1000 0001 0101 1101 1001 0011 0111 1111 1011 0010 0110 1110 1010 00 01 11 10 Z Y W

4 Variable Map Simplification F(W,X,Y,Z) = X WX 00 01 11 10 YZ 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10 00 01 11 10 Z Y W

Products-of-Sums What is the delay of products-of-sums circuit?

PopQuiz Convert 37.0310 to Octal Convert 11011.010012 to hex

Products-of-Sums What is the delay of products-of-sums circuit?

Pop Quiz F(X,Y,Z) = XY 00 01 10 11 Z 1 Z F(X,Y,Z) =

Boolean? Well almost in C Logical operators && || ! Bitwise operators ~ & | ^ << >> printf(format_str, varlist)