LCLS Timing Outline Scope The order of things

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Presentation transcript:

LCLS Timing Outline Scope The order of things Introducing the PNET VME receiver Status of the PNET VME receiver System diagram Looking at timing pulse to pulse LCLS MPG EVG Conclusions

Scope LCLS timing system is used to transmit a fiducial 360 Hz signal to all triggered devices in LCLS System requirements (speed and content) are known: receive 128 bit PNET data at 360 Hz; append add’l info; operate at 120 Hz The component parts are known: PNET VME receiver, EVG-200 and EVR-200 The interfaces are being defined

The order of things The one and only SLC Master Pattern Generator (MPG) Takes as input: 360 Hz fiducial from SLC PDU is the signal to create a new PNET buffer Performs tasks: creates PNET buffers responds to faults Outputs PNET buffers to all micros and PNET VME receiver on the next 1/360 s fiducial

Introducing the PNET VME receiver

Status of the VME PNET receiver Hardware prototype is finished (1 instance) Board is 3 slots wide to accommodate on board cable modem interface to PNET Engineering Design Specification doc written Driver and device support (bi, mbbiDirect to access each variable in PNETbuffer) written. Compiled only for Synergy PPC running RTEMS 4.6.2

System Diagram

Looking at timing pulse to pulse

Looking at timing pulse to pulse

Looking at timing pulse to pulse

LCLS MPG Takes the PNETbuffer with appended epicsTimeStamp and checksum fault indicators Adds on LCLS application commands Adds on any newly detected faults Informs EVG that data is ready

EVG On board FPGA packages/chunks 24 byte LCLS MPG data and sends to EVR at 125 MHz Data arrives in EVR in 0.6 microseconds + fiber travel time (which depends on distance)

Conclusions LCLS MPG needs to be designed LCLS MPG/EVG interface needs defining EVR/SLC-aware IOC interface needs defining Performance and reliability from PNET through to EVG must be measured But I guess there has been some progress…