1. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 Introduction Description Issues Progress Plans for 2005 SLC-Aware IOC LCLS Collaboration, April 5, 2005

2. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 SLC Alpha All High Level Apps PNet (Pulse ID / User ID) MPG SLC Net over Ethernet (Data Transfer) micro CAMAC I/O RF reference clock Xterm EPICS W/S Distributed Applications EPICS W/S Distributed Applications EPICS W/S Distributed Applications EPICS W/S Distributed Applications EPICS WS Distributed High Level Applications CA over Ethernet (EPICS Protocol) I/OC (SLC-aware) EVGEVG Micro emulator PNETPNET CAS I/OC (SLC-aware) Micro emulator Fast Feedback CA Gateway Integration with the SLC Control System

3. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 Configurations Data archive and view (History Buffer) Modeling programs (Comfort, Dimad) Correlation plots Multi-device knobs Button macros Orbit/Dispersion correction Emittance calculation Status display and logging Slow feedback control Existing VMS SLC Applications

4. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 Receive SLC messages and act on them in the same way as existing SLC micros for: BPM-Like Data Acquisition (Gated ADCs) – beam synchronous Magnet-Like Control and Readback (All Controlled Devices) PNET Timing Diagnostics Maintain its part of the VMS SLC database: Receive the entire SLC database at initialization time Receive new setpoints at any time from the Alpha Send readbacks back to the Alpha on request and periodically Send setpoint changes made by external EPICS applications to the Alpha Goal – same amount of network traffic as SLC micros SLC IOC – What It Will Do

5. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 MPS BITBUS Power Supply Control KISNET Communication Micro-to-Micro Communication via Alpha SLC-style Analog Signal Monitoring SLC-style Digital Input/Output SLC-style Error Logging (use CMLOG instead) SLC-style Klystron Interface SLC-style Video Interface SLC-style Timing Interface (except PNET diagnostics) Direct Hardware Access (and no support for “virtual CAMAC” commands) Debugging from VMS SLC-Style Fast Feedback Interface Keep static data in the EPICS and SLC database up-to-date SLC IOC – What It Won’t Do

6. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005

7. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 Piece-Meal functional requirements – big picture not always clear Endian – VMS to/from any possible EPICS platform (no 64 bit) Memory – CPUs that support SLC-aware IOC need memory Restart SLC tasks without restarting the IOC Detail diagnostics needed via the IOC shell, a subset via CA Keeping the EPICS and SLC database in-sync – 2 master problem Particularly for Magnet Control May need to increase max number of “micros” in the SLC control system May need a second proxy in the SLC production control system Applications slow in developing – need 2 people per application? SLC-Aware IOC Issues

8. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 Team: LCLS Controls: Stephanie Allison, Kristi Luchini, Consultants ESD Software: Diane Farley, Debbie Rogind, Ron MacKenzie, Consultants Weekly meetings, updates to working web page and requirements/design documentation Basic Services: Executive, Message, Database, CMLOG Services – Done except for final RTEMS testing and cleanup, identifying some new requirements (2 full- time) Async Utilities and Periodic “Micro” Health Update – Review done, implementation in-progress (1 full-time) Changes to VMS Programs – Done Updated development environment Application Services: Device Control and Readback (Magnet) – Reqts in-progress (1 part-time) PNET Timing Diagnostics – no significant progress since January Gated ADC Acquisition (BPM) – no progress Changes to VMS Programs – not yet defined Naming Conventions – First Draft done SLC IOC Progress Since January 26

9. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 2 people per application? Functional Requirements Reviews: Device Control and Readback (Magnet Job) – April PNET Timing Diags – April Gated ADC Acq (BPM Job) – June Design Reviews: Device Control and Readback (Magnet Job) – May PNET Timing Diags – Late April Gated ADC Acq (BPM Job) – July Implementation: Basic services including Async and RTEMS Testing – Mid-April Device Control and Readback – June PNET Timing Diags – June Gated ADC Acq (BPM Job) – Aug Fully operational prototype by Oct 2005 Ready for first beam in LINAC by May 2007 SLC IOC Plans for 2005

10. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 Reference Slides Follow

11. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 Introduction: SLC-Aware IOC CPUCPU EVGEVG LLRF CPUCPU EVREVR Diag IOC EVREVR HPRF I/O Boards CPUCPU EVREVR Pwr Supply Ctrl IOC SLC Alpha Apps Xterm CPUCPU Vacuum Ctrl SLC-Net over Ethernet Provides data to SLC Apps from EPICS on demand and periodically Performs requests by SLC Apps by updating EPICS Messages over Ethernet no greater than 10 Hz Requires significant development in the IOC to emulate SLC “micro” in the IOC Used by non-LCLS projects too

12. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 SLC Executive Design Block Diagram by Diane Fairley

13. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 Message Service Design Block Diagram by Diane Fairley

14. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 Database Service Design Block Diagram by Debbie Rogind

15. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 IOC CMLOG Design Block Diagram by James Silva

16. Stephanie Allison SLC-Aware IOCsaa@slac.stanford.edu April 5, 2005 Timing Beam Code + EPICS Time + EPICS Events CPUCPU EVREVR Diag 16 triggers IOC CPUCPU EVREVR Power Supply Ctrl IOC CPUCPU Vacuum Ctrl Machine Protection Drive Laser Off SLC micro 476 MHz RF Reference 128 bit beam code @ 360 Hz FIDO 119 MHz w/ 360 Hz fiducial Nsec resolution on the timing gates produced from the Event Receiver 50 psec jitter pulse to pulse PNET module gets beam code data from Master Pattern Generator Beam code data transferred to Event Generator Event generator sends events to receivers including: 360 Hz, 120 Hz, 10 Hz and 1 Hz fiducials last beam pulse OK Machine mode EPICS time stamp Event receivers produce to the IOC interrupts on events data from the event generator in registers 16 triggers with configurable delay and width CPUCPU EVGEVG LLRFLLRF 16 triggers IOC EVREVR PNETPNET MPG