Design for Testability Sungho Kang Yonsei University

Outline Introduction Testability Measure Design for Testability Ad-Hoc Testable Design Conclusion

Merging Design and Test Introduction Design and Test become closer

ASIC Market Place Gates 1992/3 1995 DFT Main 20K 60 30 No Introduction Gates 1992/3 1995 DFT Main 20K 60 30 No Stream 20-50K 30 40 Mostly No High 50K 10 30 Mostly Full Scan End 100K 1 10 Full Scan Toshiba Marketing

DFT Usage in ASIC Market Introduction 1992/3 1994 1995 No DFT 90 75 60 Scan 10 25 40 Full Scan 5 15 25 JTAG 5 20 40 BIST 5 10 20 Toshiba Marketing

Design and Test Introduction Design process

Testability Measures Testability Objective Inherent property of the circuit based on the circuit topology Probability that a fault is detected by a random vector Function of controllability and observability Controllability Ability to establish a specific signal value at each node in the circuit by setting values on the circuit inputs Observability Ability to determine the signal value at any node in a circuit by controlling primary inputs and observing its outputs Objective Estimate testability Provide guidance for redesign Provide guidance in search process of test generation Measures should be computationally simple

What Designers Want to Know Testability Will this device require an inordinate amount of time, level of effort, and/or test length in order to provide acceptable testing? Require general information about design What are the problem areas in the design where a modification can ease the testing problem? Require detailed information Testability measures might be useful Detailed information may be useful to the above question

SCOAP Sandia Controllability and Observability Analysis Program Testability Sandia Controllability and Observability Analysis Program Compute relative complexity to control and observe Combinational Node Primary input or a combinational standard cell output node Sequential Node Output node of a sequential standard cell

SCOAP 6 Numbers for Each Node, N Testability 6 Numbers for Each Node, N CC0(N): combinational 0-controllability minimum # of combinational nodes to set node N to 0 CC1(N): combinational 1-controllability minimum # of combinational nodes to set node N to 1 SC0(N): sequential 0-controllability minimum # of sequential nodes to justify 0 to node N SC1(N): sequential 1-controllability minimum # of sequential nodes to justify 1 to node N CO(N): combinational observability # of combinational nodes between N and PO and minimum # of combinational nodes to propagate a signal value on N to PO SO(N): sequential observability # of sequential nodes between N and PO and minimum # of sequential nodes to propagate a signal value on N to PO

SCOAP Initial Values for PIs and POs Buffers and Inverters PI PO Testability Initial Values for PIs and POs PI PO CC0(X) 1  CC1(X) 1  SC0(X) 0  SC1(X) 0  CO(X)  0 SO(X)  0 Buffers and Inverters Buffers Inverters CC0(Y) CC0(X)+1 CC1(X)+1 CC1(Y) CC1(X)+1 CC0(X)+1 SC0(Y) SC0(X) SC1(X) SC1(Y) SC1(X) SC0(X) CO(X) CO(Y)+1 CO(Y)+1 SO(X) SO(Y) SO(Y)

SCOAP Y = AND (X1, X2) Negative edge triggered D flip-flop with Reset Testability Y = AND (X1, X2) CC0(Y) = min[CC0(X1), CC0(X2)] + 1 CC1(Y) = CC1(X1) + CC1(X2) + 1 SC0(Y) = min[SC0(X1), SC0(X2)] SC1(Y) = SC1(X1) + SC1(X2) CO(X1) = CO(Y) + CC1(X2) + 1 SO(X1) = SO(Y) + SC1(X2) Negative edge triggered D flip-flop with Reset CC0(Q) = min [CC1(R)+CC0(C), CC0(D)+CC1(C)+CC0(C)+CC0(R)] CC1(Q) = CC1(D)+CC1(C)+CC0(C)+CC0(R) SC0(Q) = min [SC1(R)+SC0(C), SC0(D)+SC1(C)+SC0(C)+SC0(R)]+1 SC1(Q) = SC1(D)+SC1(C)+SC0(C)+SC0(R)+1 CO(D) = CO(Q)+CC1(C)+CC0(C)+CC0(R) SO(D) = SO(Q)+SC1(C)+SC0(C)+SC0(R)+1

SCOAP Fanout CC1(Y) = CC1(X) CC1(Z) = CC1(X) Testability Fanout CC1(Y) = CC1(X) CC1(Z) = CC1(X) CO(X) = min [CO(Y), CO(Z)]

SCOAP Example CC0(A) = CC1(A) = CC0(B) = CC1(B) = CC0(C) = CC1(C) = 1 Testability Example CC0(A) = CC1(A) = CC0(B) = CC1(B) = CC0(C) = CC1(C) = 1 CC0(D) = min [CC0(A), CC0(B)] + 1 = 2 CC1(D) = CC1(A) + CC1(B) + 1 = 3 CC0(E) = CC0(D) + CC0(C) + 1 = 4 CC1(E) = min [CC1(C), CC1(D)] + 1 = 2 CO(E) = 0 CO(D) = CO(E) + CC0(C) + 1 = 2 CO(C) = CO(E) + CC0(D) + 1 = 3 CO(A) = CO(D) + CC1(B) + 1 = 4 CO(B) = CO(D) + CC1(A) + 1 = 4

SCOAP Tree Problem in reconvergent fanout Optimistic Error Testability Tree Good estimate Problem in reconvergent fanout Optimistic Error Want 3/ Pessimistic Error Want 2/2

SCOAP Example CLK I DIN FB O1 O2 O3 SC0 0 0 4 4 5 6 7 Testability Example CLK I DIN FB O1 O2 O3 SC0 0 0 4 4 5 6 7 SC1 0 0 0 8 1 2 3 FB : Difficult to control Solution : Add an asynchronous reset to flip-flop FF3

Other Testability Measures TESTSCREEN # of PIs or POs that must be fixed instead of of nodes # of clock changes CAMELOT Controllability value and observability value VICTOR Combinational circuit only Emphasis an identifying redundant faults FUNTAP Functional level primitives ITTAP Selective trace capability Measure the length of sequence needed

Limitations of Testability Measures All testability measure have similar simplifying assumptions so that all results are estimates Involves the restricted information source (only circuit topology) Faults which are difficult to test cause problems Testability data provide a relatively poor indication of whether or not an individual fault will be detected by a given test

Design for Testability Difficulty in ATPG Not effective for large sequential circuits Advantages Test generation is easy High quality testing Disadvantages Area overhead Timing overhead

Classification of DFT Ad-Hoc Design Structured Design Initialization Design for Testability Ad-Hoc Design Initialization Adding extra test points Circuit partitioning Structured Design Scan design Scan Path Level Sensitive Scan Design Random Access Scan Boundary Scan Built-in Self Test

Ad Hoc Techniques Ad-Hoc Techniques which can be applied to a given product, but are not directed at solving the general problem Cost is lower than that of structured approaches (Scan, BIST, etc.) The job of doing test generation and fault simulation are usually not as simple or as straightforward

Test Points Ad-Hoc Employ test points to enhance controllability and observability Large demand on extra I/O pins Example

Test Points Ad-Hoc Multiplexing monitor points

Test Points Ad-Hoc Use demultiplexer and latch register to implement control points

Test Points Ad-Hoc Time sharing I/O ports

Test Points Candidates for control points Ad-Hoc Candidates for control points Control, address, and data bus lines on bus structured designs Enable/hold inputs to microprocessors Enable and read/write inputs to memory devices Clock and preset/clear inputs to memory devices Data select lines to multiplexers and demultiplexers Control lines on tristate devices Candidates for observation points Stem lines associated with signals having lots of fanouts Global feedback paths Redundant signal lines Outputs of logic devices having many inputs Outputs from state devices Address, control, and data buses

Initialization Design circuits to be easily initializable Ad-Hoc Design circuits to be easily initializable Initialization Process bringing a sequential circuit into a known state at some known time Circuits requiring some clever initialization sequence should be avoided Flip-flop with explicit clear Use explicit clear to all FFs

Monostable Multivibrators Ad-Hoc Disable internal one-shots during test

Oscillators and Clocks Ad-Hoc Disable internal oscillators and clocks during test Example A = 0 and B : Test input

Partitioning Ad-Hoc Partitioning shift registers into smaller units

Partitioning Ad-Hoc Split large counters

Partitioning Ad-Hoc Partitioning large circuits into small subcircuits to reduce test generation cost Example T1=0 T2=0 : Normal Mode T1=0 T2=1 : Test C1 T1=1 T2=0 : Test C2

Avoid Use of Redundant Logic Design Rule If a redundant fault occurs, it may invalidate some test for non-redundant faults Such faults cause difficulty in calculating fault coverage Much test generation time can be spent

Avoid Global Feedback Paths Design Rule Provide logic to break global feedback paths Asynchronous circuits other than latches should be avoided when possible Avoid combinational feedback loop

Avoid Gated Clock Make sure EN settles before CLK changes Design Rule Make sure EN settles before CLK changes Or redesign the circuit as follows

Bypass Counters Design Rule

Avoid Internal Pulse Generator Design Rule All internal pulse or clock generators should be isolated during test

Avoid Cross-coupled NAND/NOR Design Rule Add logic to make each cross-coupled NAND/ NOR gate behave as a transparent buffer during test

Avoid Bus Floating Design Rule Make sure each tristate bus has one pullup register, pulldown register or bus holder

Avoid Potential Bus Contention Design Rule Make sure only one tristate gate is selected at a time

Easily Testable Circuits Testable Design Aimed at developing design techniques that start with a functional specification and results that are easy to test Properties Small test sets No redundancy Tests can be found without much extra work Tests can be easily generated Faults should be locatable to the desire degree

RM Networks Read-Muller canonical form n+4 test inputs XOR cascade Testable Design Read-Muller canonical form f(x,y) = f0x’y’ + f1x’y + f2xy’ + f3xy f(x,y) = f0 (f0f2)x(f0f1)y(f0f1f2f3)xy n+4 test inputs XOR cascade Tested with 4 tests # of AND gates Tested with n tests providing an extra output The extra output is derived from an AND that has as inputs all those primary inputs that are connected to an even number of ANDs in the circuit for

RM Networks Example f=wxy’z’ + wx’z + xyz f0=wx, f1=wx’, f2=0, f3=w+x Testable Design Example f=wxy’z’ + wx’z + xyz f0=wx, f1=wx’, f2=0, f3=w+x

RM Networks Advantages Disadvantages Short test time No redundancy Testable Design Advantages Short test time No redundancy Test outputs should be easily interpreted Disadvantages Requires many gates Long delay Must be designed from boolean equations

Conclusion Ad-Hoc Design Structured Design Advantages Disadvantages Initialization Test points Partitioning Structured Design Scan design Boundary Scan Built-in Self Test Advantages Test generation is easy High quality testing Disadvantages Area overhead Timing overhead