Architecture of Microprocessor (Intel 8085) Unit-I 1

ARCHITECTURE AND FEATURES OF 8085 MICROPROCESSOR 8085 was introduced in 1977 It is 8-bit Microprocessor Actual Name is 8085A It contains 6200 Transistors It has 40-pin Dual-in-Line Package Its Dimension is 164mmx222mm

Intel 8085 Pin Configuration 3

Signals Groups and I/O Pins

The 8085 and Its Buses The 8085 is an 8-bit general purpose microprocessor that can address 64K Byte of memory. It has 40 pins and uses +5V for power. It can run at a maximum frequency of 3 MHz. The pins on the chip can be grouped into 6 groups: Address Bus. Data Bus. Control and Status Signals. Power supply and frequency. Externally Initiated Signals. Serial I/O ports. 6

The Address and Data Bus Systems The address bus has 8 signal lines A8 – A15 which are unidirectional. The other 8 address bits are multiplexed (time shared) with the 8 data bits. So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the same time. During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits. In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes.

The Control and Status Signals There are 4 main control and status signals. These are: ALE: Address Latch Enable. This signal is a pulse when that become 1 the AD0 – AD7 lines have an address on them. It becomes 0 after that. This signal can be used to enable a latch to save the address bits from the AD lines. RD: Read. Active low. WR: Write. Active low. IO/M`: This signal specifies whether the operation is a memory operation (IO/M`=0) or an I/O operation (IO/M`=1). S1 and S0 : Status signals to specify the kind of operation being performed. Usually not used in small systems.

ALE used to de-multiplex address/data bus

Frequency Control Signals There are 3 important pins in the frequency control group. X0 and X1 are the inputs from the crystal or clock generating circuit. The frequency is internally divided by 2 using PLL. So, to run the microprocessor at 3 MHz, a clock running at 6 MHz should be connected to the X0 and X1 pins. CLK (OUT): An output clock pin to drive the clock of the rest of the system. We will discuss the rest of the control signals as we get to them.

The ALU In addition to the arithmetic & logic circuits, the ALU includes an accumulator, which is a part of every arithmetic & logic operation. Also, the ALU includes a temporary register used for holding data temporarily during the execution of the operation. This temporary register is not accessible by the programmer.

Register and Register Pair

Flag Register X Sign Carry Zero Parity Auxiliary Carry X - Unspecified AC P C Sign Carry Zero Parity Auxiliary Carry X - Unspecified

The Flags register There is also a flag register whose bits are affected by the arithmetic & logic operations. S-sign flag The sign flag is set if bit D7 of the accumulator is set after an arithmetic or logic operation. Z-zero flag Set if the result of the ALU operation is 0. Otherwise is reset. This flag is affected by operations on the accumulator as well as other registers. (DCR B). AC-Auxiliary Carry This flag is set when a carry is generated from bit D3 and passed to D4 . This flag is used only internally for BCD operations. P-Parity flag After an ALU operation, if the result has an even number of 1s, the p-flag is set. Otherwise it is cleared. So, the flag can be used to indicate even parity. CY-carry flag This flag is set when a carry is generated from bit D7 after an unsigned operation. OV-Overflow flag This flag is set when an overflow occurs after a signed operation.

Connection of different units and bus systems A15-A8 Latch AD7-AD0 D7- D0 A7- A0 8085 ALE IO/M RD WR 1K Byte Memory Chip CS A9- A0 A15- A10 Chip Selection Circuit

8085 Machine Cycles The 8085 executes several types of instructions with each requiring a different number of operations of different types. However, the operations can be grouped into a small set. The three main types are: Memory Read and Write. I/O Read and Write. Request Acknowledge. These can be further divided into various smaller operations (machine cycles).

Opcode Fetch Machine Cycle The first step of executing any instruction is the Opcode fetch cycle. In this cycle, the microprocessor brings in the instruction’s Opcode from memory. To differentiate this machine cycle from the very similar “memory read” cycle, the control & status signals are set as follows: IO/M=0, S0 and S1 are both 1. This machine cycle has four T-states. The 8085 uses the first 3 T-states to fetch the opcode. T4 is used to decode and execute it. It is also possible for an instruction to have 6 T-states in an opcode fetch machine cycle.

Memory Read Machine Cycle The memory read machine cycle is exactly the same as the opcode fetch except: It only has 3 T-states The s0 signal is set to 0 instead.

The Memory Read Machine Cycle To understand the memory read machine cycle, let’s study the execution of the following instruction: MVI A, 32 In memory, this instruction looks like: The first byte 3EH represents the opcode for loading a byte into the accumulator (MVI A), the second byte is the data to be loaded. The 8085 needs to read these two bytes from memory before it can execute the instruction. Therefore, it will need at least two machine cycles. The first machine cycle is the opcode fetch discussed earlier. The second machine cycle is the Memory Read Cycle. 2000H 3E 2001H 32

The Memory Write Operation In a memory write operation: The 8085 places the address (2065H) on the address bus Identifies the operation as a ‘memory write’ (IO/M=0, s1=0, s0=1). Places the contents of the accumulator on the data bus and asserts the signal WR. During the last T-state, the contents of the data bus are saved into the memory location.

Machine Cycles vs. Number of bytes in the instruction Machine cycles and instruction length, do not have a direct relationship. To illustrate, let’s look at the machine cycles needed to execute the following instruction. STA 2065H This is a 3-byte instruction requiring 4 machine cycles and 13 T-states. The machine code will be stored in memory as shown to the right This instruction requires the following 4 machine cycles: A ‘Opcode fetch’ to fetch the opcode (32H) from location 2010H, ‘decode’ it and determine that 2 more bytes are needed (4 T-states). A ‘Memory read’ to read the low order byte of the address (65H) (3 T- states). A ‘Memory read’ to read the high order byte of the address (20H) (3 T-states). A ‘memory write’ to write the contents of the accumulator into the memory location. 32H 2010H 65H 2011H 20H 2012H

The Overall Picture 8085 A15- A10 A15-A8 A9- A0 A7- A0 D7- D0 ALE Latch AD7-AD0 D7- D0 A7- A0 8085 ALE IO/M RD WR 1K Byte Memory Chip CS A9- A0 A15- A10 Chip Selection Circuit

Control and Status Signals.

8085 μp has several interrupt signals as shown in the following table.

Note: * the address of the ISR is determined by the external hardware. Interrupt signals An interrupt is a hardware-initiated subroutine CALL. When interrupt pin is activated, an ISR will be called, interrupting the program that is currently executing. Pin Subroutine Location TRAP 0024 RST 5.5 002C RST 6.5 0034 RST 7.5 003C INTR * Note: * the address of the ISR is determined by the external hardware.

Interrupt signals INTR input is enabled when EI instruction is executed. The status of the RST 7.5, RST 6.5 and RST 5.5 pins are determined by both EI instruction and the condition of the mask bits in the interrupt mask register.

Interrupt Vectors

A circuit that causes an RST4 instruction (E7) to be executed in response to INTR. When INTR is asserted, 8085 response with INTA pulse. During INTA pulse, 8085 expect to see an instruction applied to its data bus.

RESET signal Following are the two kind of RESET signals: RESET IN: an active low input signal, Program Counter (PC) will be set to 0 and thus MPU will reset. RESET OUT: an output reset signal to indicate that the μp was reset (i.e. RESET IN=0). It also used to reset external devices.

RESET signal

Direct Memory Access (DMA) DMA is an IO technique where external IO device requests the use of the MPU buses. Allows external IO devices to gain high speed access to the memory. Example of IO devices that use DMA: disk memory system. HOLD and HLDA are used for DMA. If HOLD=1, 8085 will place it address, data and control pins at their high-impedance. A DMA acknowledgement is signaled by HLDA=1.

MPU Communication and Bus Timing Moving data form memory to MPU using MOV instruction

MPU Communication and Bus Timing The Fetch Execute Sequence : The μp placed a 16 bit memory address from PC (program counter) to address bus. at T1 The high order address, 20H, is placed at A15 – A8. the low order address, 05H, is placed at AD7 - AD0 and ALE is active high. Synchronously the IO/M is in active low condition to show it is a memory operation. At T2 the active low control signal, RD, is activated so as to activate read operation; it is to indicate that the MPU is in fetch mode operation. T3: The active low RD signal enabled the byte instruction, 4FH, to be placed on AD7 – AD0 and transferred to the MPU. While RD high, the data bus will be in high impedance mode. T4: The machine code, 4FH, will then be decoded in instruction decoder. The content of accumulator (A) will then copied into C register at time state, T4.

MPU Communication and Bus Timing 8085 timing diagram for Opcode fetch cycle for MOV 34

Memory Interfacing There needs to be a lot of interaction between the microprocessor and the memory for the exchange of information during program execution. Memory has its requirements on control signals and their timing. The microprocessor has its requirements as well. The interfacing operation is simply the matching of these requirements.

Memory Structure & Its Requirements Address Lines Data Lines CS RD Output Buffer RAM WR Input Buffer ROM Address Lines Date CS RD Output Buffer The way of interfacing the above two chips to the microprocessor is the same. However, the ROM does not have a WR signal.

Memory Interfacing Accessing memory can be summarized into the following three steps: Select the chip. Identify the memory register. Enable the appropriate buffer. Translating this to microprocessor domain: The microprocessor places a 16-bit address on the address bus. Part of the address bus will select the chip and the other part will go through the address decoder to select the register. The signals IO/M and RD combined indicate that a memory read operation is in progress. The MEMR signal can be used to enable the RD line on the memory chip.

Address decoding The result of ‘address decoding’ is the identification of a register for a given address. A large part of the address bus is usually connected directly to the address inputs of the memory chip. This portion is decoded internally within the chip. What concerns us is the other part that must be decoded externally to select the chip. This can be done either using logic gates or a decoder.

The Design and Operation of Memory Memory in a microprocessor system is where information (data and instructions) is kept. It can be classified into two main types: Main memory (RAM and ROM) Storage memory (Disks , CD ROMs, etc.) The simple view of RAM is that it is made up of registers that are made up of flip-flops (or memory elements). The number of flip-flops in a “memory register” determines the size of the memory word. ROM on the other hand uses diodes instead of the flip-flops to permanently hold the information.

Accessing Information in Memory For the microprocessor to access (Read or Write) information in memory (RAM or ROM), it needs to do the following: Select the right memory chip (using part of the address bus). Identify the memory location (using the rest of the address bus). Access the data (using the data bus).

An important circuit element that is used extensively in memory. Tri-State Buffers An important circuit element that is used extensively in memory. This buffer is a logic circuit that has three states: Logic 0, logic1, and high impedance. When this circuit is in high impedance mode it looks as if it is disconnected from the output completely. The Output is Low The Output is High High Impedance

The Tri-State Buffer This circuit has two inputs and one output. The first input behaves like the normal input for the circuit. The second input is an “enable”. If it is set high, the output follows the proper circuit behavior. If it is set low, the output looks like a wire connected to nothing. OR Input Output Input Output Enable Enable

The Basic Memory Element The basic memory element is similar to a D latch. This latch has an input where the data comes in. It has an enable input and an output on which data comes out. Data Input Data Output D Q Enable EN

The Basic Memory Element However, this is not safe. Data is always present on the input and the output is always set to the contents of the latch. To avoid this, tri-state buffers are added at the input and output of the latch. Data Input Data Output D Q WR RD Enable EN

A Memory “Register” If we take four of these latches and connect them together, we would have a 4-bit memory register. I0 I1 I2 I3 WR D D D D Q Q Q Q EN EN EN EN EN RD O0 O1 O2 O3

A group of memory registers Expanding on this scheme to add more memory registers we get the diagram to the right.

A group of Memory Registers If we represent each memory location (Register) as a block we get the following I0 I1 I2 I3 WR Input Buffers EN0 Memory Reg. 0 EN1 Memory Reg. 1 EN2 Memory Reg. 2 EN3 Memory Reg. 3 RD Output Buffers O0 O1 O2 O3

The Design of a Memory Chip Using the RD and WR controls we can determine the direction of flow either into or out of memory. Then using the appropriate Enable input we enable an individual memory register. What we have just designed is a memory with 4 locations and each location has 4 elements (bits). This memory would be called 4 X 4 [Number of location X number of bits per location].

The Design of a Memory Chip So, the previous diagram would now look like the following: I0 I1 I2 I3 WR Input Buffers A d r e s D e c o d r Memory Reg. 0 A1 Memory Reg. 1 Memory Reg. 2 A0 Memory Reg. 3 RD Output Buffers O0 O1 O2 O3

The Design of a Memory Chip Since we have tri-state buffers on both the inputs and outputs of the flip flops, we can actually use one set of pins only. The chip would now look like this: WR Input Buffers A d r e s D e c o d r D0 D0 Memory Reg. 0 A1 A1 Memory Reg. 1 D1 D1 Memory Reg. 2 A0 D2 A0 D2 Memory Reg. 3 D3 D3 RD Output Buffers RD WR

# of memory locations = 2( # of address lines) Dimensions of Memory Memory is usually measured by two numbers: its length and its width (Length X Width). The length is the total number of locations. The width is the number of bits in each location. The length (total number of locations) is a function of the number of address lines. # of memory locations = 2( # of address lines) So, a memory chip with 10 address lines would have 210 = 1024 locations (1K) Looking at it from the other side, a memory chip with 4K locations would need Log2 4096=12 address lines

The 8085 and Memory The 8085 has 16 address lines. That means it can address 216 = 64K memory locations. Then it will need 1 memory chip with 64 k locations, or 2 chips with 32 K in each, or 4 with 16 K each or 16 of the 4 K chips, etc. how would we use these address lines to control the multiple chips?

Chip Select Usually, each memory chip has a CS (Chip Select) input. The chip will only work if an active signal is applied on that input. To allow the use of multiple chips in the make up of memory, we need to use a number of the address lines for the purpose of “chip selection”. These address lines are decoded to generate the 2n necessary CS inputs for the memory chips to be used.

Chip Selection Example RD WR D0 D1 RD WR RD WR RD WR RD WR A0 A0 A0 A0 A1 A1 A1 A1 CS CS CS CS A0 A1 2 X4 Decoder A2 A3

Memory Map and Addresses The memory map is a picture representation of the address range and shows where the different memory chips are located within the address range. 0000 0000 EPROM Address Range of EPROM Chip 3FFF 4400 RAM 1 Address Range of 1st RAM Chip 5FFF RAM 2 6000 Address Range of 2nd RAM Chip Address Range 8FFF 9000 RAM 3 Address Range of 3rd RAM Chip A3FF RAM 4 A400 Address Range of 4th RAM Chip F7FF FFFF

The 8085 and Address Ranges The 8085 has 16 address lines. So, it can address a total of 64K memory locations. If we use 64 memory chips with 1K locations each, then we will need 64 such chips. The 1K memory chip needs 10 address lines to uniquely identify the 1K locations. (log21024 = 10) That leaves 6 address lines which is the exact number needed for selecting between the 64 different chips (log264 = 6).

Location Selection within the Chip The 8085 and Address Ranges Now, we can break up the 16-bit address of the 8085 into two pieces: A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Depending on the combination on the address lines A15 - A10 , the address range of the specified chip is determined. Chip Selection Location Selection within the Chip

Chip Select Example A chip that uses the combination A15 - A10 = 001000 would have addresses that range from 2000H to 23FFH. Keep in mind that the 10 address lines on the chip gives a range of 00 0000 0000 to 11 1111 1111 or 000H to 3FFH for each of the chips. The memory chip in this example would require the following circuit on its chip select input:

Chip Select Example If we change the above combination to the following: Now the chip would have addresses ranging from: 2400 to 27FF. Changing the combination of the address bits connected to the chip select changes the address range for the memory chip.

High-Order vs. Low-Order Address Lines The address lines from a microprocessor can be classified into two types: High-Order Used for memory chip selection Low-Order Used for location selection within a memory chip. This classification is highly dependent on the memory system design.

Data Lines All of the above discussion has been regarding memory length. Lets look at memory width. We said that the width is the number of bits in each memory word. We have been assuming so far that our memory chips have the right width. What if they don’t? It is very common to find memory chips that have only 4 bits per location. How would you design a byte wide memory system using these chips? We use two chips for the same address range. One chip will supply 4 of the data bits per address and the other chip supply the other 4 data bits for the same address.

Data Lines CS A0 … A9 CS CS D0 … D3 D4 … D7