Roberto Dinapoli CERN-CEM II,Montpellier For the ALICE Collaboration The Alice Silicon Pixel Redout System – Moving towards system integration Roberto Dinapoli CERN-CEM II,Montpellier For the ALICE Collaboration Colmar, 9-13 September 2002

Thanks to all the ALICE SPD Group!! And in particular, for their contributions to the present talk: Petra Riedler (Test beam, wafer probing) Peter Chochula (Test system) Michel Morel (Bus) Alex Kluge (Digital Pilot Chip and MCM) M. Campbell, Ken Wyllie (LHCBPIX1) Giorgio Stefanini

Outline The Alice Silicon Pixel Detector System The front-end chip The readout system and its components The test system The 2002 test beam Conclusions

The Alice Silicon Pixel Detector 2 barrel layers Dz= 28.3 cm r= 3.9 cm & 7.6 cm Image: INFN Padova

The Alice Silicon Pixel Detector: the front-end pixel chip Mixed mode signal (analogue, digital) 256 rows 32 columns (8192 channels) 13 million transistors Designed to serve ALICE and LHCb 10MHz clock 1.8V power supply ~100W/channel 13.5 mm 15.8 mm

The Alice Silicon Pixel Detector: the ladder and the singles Five chips Single chip Bump Bonding Bump Bonding Ladder detector (12.8 x 69.6 mm2 active area) single chip detector (12.8 x 13.6 mm2 active area) Detector Chips: 750 µm thick, target: 150 µm Detectors: p-in-n 300 µm/200 µm thickness Chip Bump-bonding: VTT/Finland Pb-Sn solder bumps AMS/Italy In bumps

The Alice Silicon Pixel Detector: the half stave and the stave ± 193 mm ladder1 ladder2 70.72 mm MCM Control,readout and and auxiliary chips: Analog Pilot Digital pilot GOL Optical links Stave In total: 60 staves 240 ladders 1200 chips 9.83 E6 active channels

The Alice Silicon Pixel Detector: the sector The ALICE SPD One carbon-fibre support for Layer 1+2 Image: INFN Padova readout of 120 half-staves in parallel ladder 4 staves in layer 2 2 staves in layer 1

ALICE1LHCb pixel cell 125mm pre-amp (differential) shaper (differential) discriminator (+ fast-OR, fast-MULT) 65mW static consumption 265mm two digital delay units trigger coincidence logic 4-event FIFO buffer readout logic 35mm 5 un-upsettable latches for configuration test input on/off pixel mask on/off 3 bits of threshold adjust

Pixel Front End: preamplifier-shaper IN PREAMPLIFIER SHAPER #1 SHAPER #2 Cfb r FEEDBACK STAGE gmf A2 p2 A3 p3 Closed loop poles (s plane) j p1 x p3 x  p2 x fb=20 ns p2=5 ns Simplified equation: Cfb fb = A2 gmf p1-2=(8050j) Mrad/s s2 p2 fb+ s fb +1=0 p3=13.5 ns

Radiation Tolerance Total Ionizing Dose: Single Event Effects: Studied at Louvain-la-Neuve No SEGR nor SEL observed Measure SEU rate indicates that in Alice environment it will not exceed 1bit/10hours of operation for the full detector (calculated for all DACs in SPD) Total Ionizing Dose: Studied at CERN-MIC irradiation facility Total expected dose: 2.5kGy Design tolerance: 5 kGy Tested tolerance: >100kGy NOTE: ALL the asics in the barrel were designed in 0.25m CMOS technology using special layout and design techniques to obtain radiation tolerance

Front-end results MEASURED: Gain: ~2 mV/100e- Peaking time: ~35ns Power consumption: ~0.6W (@1.6V) Noise: ~180e- ½ shaper Problems: Pulser,Output buffers CORRECTED: preamp Gain: ~3 mV/100e- Peaking time: ~27ns Noise: ~120e-

Threshold distribution (no threshold adjust) and noise Threshold Scan Pulse each row (e.g. 250 triggers) with test-pulse (e.g. 0-50 mV) Determined from S-curve. Mean minimum threshold: ~1000 e-, ~ 200 e- RMS Mean noise:~120 e-

Wafers Wafer probing Yield of class I chips: ~35-70% On our wafer prober we can test: single chips, assemblies, ladders, wafers 8” wafers (200 mm diameter) Each wafer contains 86 ALICE1LHCb chips (chip-size: 15.8 x 13.5 mm2) Tests for each chip: Power supply currents JTAG functionality DAC scans Configuration registers functionality Minimum threshold Threshold Scan Yield of class I chips: ~35-70%

First Ladder Tests - VTT Chip 57 Chip 58 Chip 65 Chip 67 Chip 75 Cd-measurement VTT Ladder2: Detector: 3.1µA @ 80V Pixels with hits: chip Sr Cd 75 98.5 % 97.9 % 3 noisy pixel 67 94.1 % 94.2 % 2 noisy pixel 65 99.4 % 99.2 % 58 99.5 % 57 99.4% 1 noisy column

The Readout System Control Room Pixel Bus Pilot MCM p i x e l r o u t Digital Pilot Chip 9 l p i x e l t r a n s m i t e p i Converter and control daughter card x i h p c s e r i a l i z e r & G - l i n k i o p t i c s l i n k p i x e l . r e c e i v e r c o n v e r t e r p i x e l b u s y , j t a g l r o u t e r e p x i i h L 1 , L 2 y , L 2 n , p c p i x e l c o n t r o l t e s t p u l s e , j t a g Analog Pilot r e c e i v e p i x e l c o n t r o l t r a n s m i t Temp. Sensors Control Room Pixel Bus Pilot MCM

The Analog Pilot Chip Designed by G. Anelli, R. Dinapoli, A. Kluge Submitted: 19 April 2002 First tests started beginning August 2002 Only 2 boards available, new board in production Mixed mode Power supply: 2.5 V Power consumption (clocked): ~50mW 4 mm 2 mm

The Analog Pilot Chip: the architecture Six 8-bit DACs for biasing the pixel chip One 10-bit ADC (with a 16-input multiplexer) to monitor: Temperature Power Supplies Pixel chip DAC outputs Analog Pilot chip DAC outputs Current sources for T monitoring Voltage references for the on-chip DACs and ADC (can be bypassed) JTAG controller

The Analog Pilot Chip: first results References Reference name Simul. Meas. DAC_REF_MID 0.56 0.558 DAC_REF_VDD 1 0.998 ADC_ref_0 0.513 0.512 ADC_ref_1 1.925 1.918 v_bias 1.16 1.153 All references work well Five out of six DACs work well Still to be tested: Multiplexer + ADC Temperature monitoring The JTAG and the digital part seem to work well

The Readout System Control Room Pixel Bus Pilot MCM Digital Pilot Chip - l i n k s e r a z & o p t c Digital Pilot Chip L 1 , 2 y u j g x h 9 v b m Analog Temp. Sensors . Pixel Bus Pilot MCM Control Room Converter and control daughter card

The GOL Chip and the Digital Pilot Chip Gigabit Optical Link serializer Receives control signals from the control room Controls all the chips on the MCM via JTAG Reads data from the chips and sends them to the GOL chip First prototype tested and fully functional Translates data into Glink compatible 800Mbit/s stream of data on an optical link, which will provide the connection from the MCM to the control room It was already developed at CERN It’s tested and fully functional

Digital pilot test board Optical link (clk, data) Pilot chip Deserializer Fast G-link Trigger/DAQ Pixel chip GOL chip

The MCM First Prototype of the MCM board is ready 5cm Digital Pilot GOL chip Analog Pilot Lasers and PIN diodes

The SPD Bus 240µm Wire bonds to the ALICE1LHCb chip PIXEL DETECTOR ± 193 mm ladder2 ladder1 Power supplies connector Extenders (Copper-capton) Flexible Extender MCM 70.72 mm 70.72 mm 1000mm 1 2 3 4 5 6 READOUT CHIP PIXEL DETECTOR Aluminum Polyimide Glue COOLING TUBE 11mm 2mm 7 SMD component 240µm Wire bonds to the ALICE1LHCb chip 7 layers Al-Kapton flex Michel Morel EP/ED

The SPD Bus As of today, we successfully tested: First Bus prototype with 10 mounted chips Ladder with 5 chips mounted on bus (with beam) Waiting for the Second Bus prototype M. Morel

The pixel test system components VME Master JTAG Controller Pixel Carrier R/O Controller Pixel Carrier Pixel Chip P. Chochula DAQ Adapter DAQ Adapter Modular System based on VME Designed for wafer probing, chip, assemblies, ladders, bus studies and test beams Control software based mainly on Windows and LabView

The test system software This is the test beam version of the software

Pixel Test beams July and September 2001 July 2002 3 detector planes with single chip assemblies Studies of chip efficiency, thresholds and timings July 2002 5 detector planes in the beam (2 mini busses and a DUT) Tests of a thick assembly (300m) Tests of thin assembly (200m) Tests of a ladder (300m) Collection of data for simulation models tuning

The Test beam Setup Minibus Tested Object Minibus Scintillators

Online Measurements Ladder Thin assembly Bias Scan Threshold-scan

Conclusions The Front End chip has been extensively tested, and is now qualified to be used in the experiment Assemblies and ladders have been produced and successfully tested with source measurements and during test beams (2001 and 2002) All the components of the MCM are ready, even if they are still prototype versions The first bus with 10 chips was successfully tested The test system proved to be robust and extremely flexible Next step: test of a half stave on a dedicated board