7 December 2011Powering Smartphone SoCs with Multichannel TSV DRAMs1 3D Mania: Powering Smartphone SoCs with Multichannel TSV DRAMs Drew Wingard, Sonics

7 December 2011Powering Smartphone SoCs with Multichannel TSV DRAMs2 Concurrency in Smartphone SoCs H.264 Decode Audio Decode Video Out Transport demux Smartphone SoCs process data in parallel, but communicate…

7 December 2011Powering Smartphone SoCs with Multichannel TSV DRAMs3 Concurrency in Smartphone SoCs H.264 Decode Audio Decode Video Out Transport demux DRAM

6 July 2011MPSoC '11: Leveraging 3D Multichannel DRAMs © 2011 Sonics, Inc.4 Smartphone Problems and Opportunities ■Problems in current systems In mobile SoCs, DRAM bandwidth needs grow faster than capacity needs Scaling DRAM bandwidth requires extra DRAMs o And power-hungry PHYs Wider DRAM interfaces & deeper pipelining increases access granularity, driving need for multichannel approaches o Which causes extra pin costs (after 2 channels) Current DRAM interfaces are a bottleneck between o Lots of parallel initiators (data clients) o Lots of parallel DRAM banks (data servers) ■What if we could get rid of the interface bottleneck? And be limited by DRAM bank bandwidths, instead Without needing fancy PHYs

6 July 2011MPSoC '11: Leveraging 3D Multichannel DRAMs © 2011 Sonics, Inc.5 Wide I/O: TSV-enabled Mobile DRAM ■Pending JEDEC standard (JC 42.6) ■High bandwidth, even at low capacity Like 4 (x32) channels of LPDDR GBytes/sec peak bandwidth ■Lowest power No PHY (simple drivers/receivers, no PLL/DLL) Low loading (capacitance and inductance) Modest frequency (200 MHz) ■Smallest form factor 3D stacked based on thin (50µm) TSV-based die ■Minimal change to DRAM design (ex-TSV) ■Risks are all TSV-related (cost, yield, biz model) ■Smartphone market will drive volumes

6 July 2011MPSoC '11: Leveraging 3D Multichannel DRAMs © 2011 Sonics, Inc.6 Wide I/O Power Estimates Sophie Dumas, ST-E JEDEC Mobile Memory Forum June 2011 (Taiwan)

6 July 2011MPSoC '11: Leveraging 3D Multichannel DRAMs © 2011 Sonics, Inc.7 Multichannel DRAM System Challenges Application View Physical Organization Key Problems: ■Load balancing Must balance memory traffic evenly among channels ■Maintaining throughput Multiple channels cause throughput & ordering issues for pipelined memories Software and IP cores must manage multiple channels explicitly

7 December 2011Powering Smartphone SoCs with Multichannel TSV DRAMs8 Locality Challenges: DRAM Access Styles ■Exploiting spatial locality is key for high utilization CPUs tend to stay with an O/S page (multiple DRAM pages) Much processing and I/O DMA uses long incrementing bursts Image processing is tougher ■Two-dimensional bursts 2D transaction using a single OCP read or write command Popular for HD video and graphics ■Address tiling Rearrange DRAM address organization to exploit locality Avoids page misses One size doesn’t fit all!

6 July 2011MPSoC '11: Leveraging 3D Multichannel DRAMs © 2011 Sonics, Inc.9 Interleaved Multichannel Technology (IMT*): Seamless Transition to Multichannel ■Interleaving support requires splitting (and chopping!) traffic for delivery to proper channel Splitting in memory controller creates performance and routing congestion bottleneck ■Predictably high performance Automatically spreads traffic across channels to ensure load balancing Keeps DRAMs operating at full throughput without costly reorder buffers ■Scalable architecture Up to 8 interleaved channels within the same address region Fully distributed to avoid bottlenecks & placement restrictions ■Application flexibility Transparent to software and initiator hardware Supports full or partial memory configurations – at run time Multichannel Interleaving in the Interconnect Higher Performance, Lower Area, More Scalable *patents pending

7 December 2011Powering Smartphone SoCs with Multichannel TSV DRAMs10 Transparent Multichannel Interleaving with Access-Optimized Boundaries Application View Physical Organization Independent Interleaving Size Support

7 December 2011Powering Smartphone SoCs with Multichannel TSV DRAMs11 MemMax™ Memory Scheduler Multi-threaded & multi-tagged OCP with non-blocking flow control In-order with early pre-charge/activate Compiled (SRAM) data buffers decouple rates & cross clock domain ■Address tiling ■Request grouping ■2D burst support ■Guaranteed bandwidth QoS with demotion ■Per-thread buffer sizing ■Run time re-programmable

6 July 2011MPSoC '11: Leveraging 3D Multichannel DRAMs © 2011 Sonics, Inc.12 Complete Wide I/O System Solution Sonics Interconnect with IMT Video Pre Processor Graphics Engine Video Decoder Video Post Processor Transport Engine IA Host CPU Audio Processor Streaming Processor Debug Interface IA Wide I/O Controller 0 MemMax 0 TA MemMax 3 Wide I/O Controller 3 Wide I/O DRAM TA GPIO USBFLASH TA SRAM TA Storage SOC TA ■Channel splitting and load balancing ■Scheduling for high efficiency & QoS ■Wide I/O interface

October 11, 2011© Sonics, Inc., 2011, All rights reserved, NDA required13 Power Domain Partitioning CPU1 CPU0 MemMax DRAM Controller Encrypt Engine GPU Flash Cntr Face Detection Video Codec Camera Cntr DMA Cntr HSI MMC SD USB Cntr UART SPI Timer Clk Mgr GPIO BootROM Audio Codec Misc Touch Cntr Power Mgr Accel INTC Digital Compass L2 Cache Power Domain 1 Power Domain 4 Power Domain 3 Power Domain 2 Sonics Peripheral Network SonicsGN Network on Chip Advanced Partitioning Multiple Clocks Efficient power Mgmt Better timing closure

6 July 2011MPSoC '11: Leveraging 3D Multichannel DRAMs © 2011 Sonics, Inc.14 Summary ■Smartphone SoC performance dominated by DRAM ■New JEDEC Wide I/O standard offers compelling performance and power benefits Assuming TSV-related issues can be managed ■3D smartphone SoC solutions require: Massive connectivity Transparent multi-channel DRAM load balancing High-efficiency DRAM scheduling with high QoS Minimum energy usage

7 December 2011Powering Smartphone SoCs with Multichannel TSV DRAMs15 THANK YOU!