HISTORY OF MICROPROCESSORS Gursharan Singh Tatla 1.

Slides:



Advertisements
Similar presentations
Advanced Piloting Cruise Plot.
Advertisements

1
Copyright © 2003 Pearson Education, Inc. Slide 1 Computer Systems Organization & Architecture Chapters 8-12 John D. Carpinelli.
Chapter 1 The Study of Body Function Image PowerPoint
Copyright © 2013 Elsevier Inc. All rights reserved.
Copyright © 2011, Elsevier Inc. All rights reserved. Chapter 6 Author: Julia Richards and R. Scott Hawley.
Author: Julia Richards and R. Scott Hawley
1 Copyright © 2013 Elsevier Inc. All rights reserved. Appendix 01.
1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 3 CPUs.
Properties Use, share, or modify this drill on mathematic properties. There is too much material for a single class, so you’ll have to select for your.
Multiplication X 1 1 x 1 = 1 2 x 1 = 2 3 x 1 = 3 4 x 1 = 4 5 x 1 = 5 6 x 1 = 6 7 x 1 = 7 8 x 1 = 8 9 x 1 = 9 10 x 1 = x 1 = x 1 = 12 X 2 1.
Division ÷ 1 1 ÷ 1 = 1 2 ÷ 1 = 2 3 ÷ 1 = 3 4 ÷ 1 = 4 5 ÷ 1 = 5 6 ÷ 1 = 6 7 ÷ 1 = 7 8 ÷ 1 = 8 9 ÷ 1 = 9 10 ÷ 1 = ÷ 1 = ÷ 1 = 12 ÷ 2 2 ÷ 2 =
UNITED NATIONS Shipment Details Report – January 2006.
1 RA I Sub-Regional Training Seminar on CLIMAT&CLIMAT TEMP Reporting Casablanca, Morocco, 20 – 22 December 2005 Status of observing programmes in RA I.
Jeopardy Q 1 Q 6 Q 11 Q 16 Q 21 Q 2 Q 7 Q 12 Q 17 Q 22 Q 3 Q 8 Q 13
CALENDAR.
FACTORING ax2 + bx + c Think “unfoil” Work down, Show all steps.
Year 6 mental test 5 second questions
Year 6 mental test 10 second questions
Around the World AdditionSubtraction MultiplicationDivision AdditionSubtraction MultiplicationDivision.
£1 Million £500,000 £250,000 £125,000 £64,000 £32,000 £16,000 £8,000 £4,000 £2,000 £1,000 £500 £300 £200 £100 Welcome.
REVIEW: Arthropod ID. 1. Name the subphylum. 2. Name the subphylum. 3. Name the order.
Introduction to Microprocessors
Buses are strips of parallel wires or printed circuits used to transmit electronic signals on the systemboard to other devices. Most Pentium systems use.
Prof. Muhammad Saeed. "The number of transistors incorporated in a chip will approximately double every 24 months." Moors Law.
Introduced 1982 Used mostly in embedded applications - controllers, point-of- sale systems, terminals, and the like Used in several MS-DOS non-PC- Compatible.
Figure 12–1 Basic computer block diagram.
Microprocessor A microprocessor also called the CPU is the heart of the computer system or any computing device. It is a semiconductor chip which can be.
PP Test Review Sections 6-1 to 6-6
EU market situation for eggs and poultry Management Committee 20 October 2011.
EU Market Situation for Eggs and Poultry Management Committee 21 June 2012.
Produced From 1978 to 1990s Common manufacturer(s) Intel Max CPU clock5 MHz to 10 MHz Instruction setx86-16 Package(s) 40 pin DIP.
80x86.
CS 6143 COMPUTER ARCHITECTURE II SPRING 2014 ACM Principles and Practice of Parallel Programming, PPoPP, 2006 Panel Presentations Parallel Processing is.
VOORBLAD.
Copyright © 2012, Elsevier Inc. All rights Reserved. 1 Chapter 7 Modeling Structure with Blocks.
1 RA III - Regional Training Seminar on CLIMAT&CLIMAT TEMP Reporting Buenos Aires, Argentina, 25 – 27 October 2006 Status of observing programmes in RA.
Factor P 16 8(8-5ab) 4(d² + 4) 3rs(2r – s) 15cd(1 + 2cd) 8(4a² + 3b²)
Basel-ICU-Journal Challenge18/20/ Basel-ICU-Journal Challenge8/20/2014.
1..
CONTROL VISION Set-up. Step 1 Step 2 Step 3 Step 5 Step 4.
© 2012 National Heart Foundation of Australia. Slide 2.
Understanding Generalist Practice, 5e, Kirst-Ashman/Hull
Before Between After.
Model and Relationships 6 M 1 M M M M M M M M M M M M M M M M
25 seconds left…...
Subtraction: Adding UP
Equal or Not. Equal or Not
Slippery Slope
Gursharan Singh Tatla PIN DIAGRAM OF 8086 Gursharan Singh Tatla Gursharan Singh Tatla
Januar MDMDFSSMDMDFSSS
Analyzing Genes and Genomes
©Brooks/Cole, 2001 Chapter 12 Derived Types-- Enumerated, Structure and Union.
Essential Cell Biology
Intracellular Compartments and Transport
PSSA Preparation.
Essential Cell Biology
1 Chapter 13 Nuclear Magnetic Resonance Spectroscopy.
Energy Generation in Mitochondria and Chlorplasts
HISTORY OF MICROPROCESSORS
Microprocessors BY Sandy G.
Lecture 3 Dr. Muhammad Ayaz Computer Organization and Assembly Language. (CSC-210)
HISTORY OF MICROPROCESSORS
HISTORY OF MICROPROCESSORS
HISTORY OF MICROPROCESSORS
Lecture 3 (Microprocessor)
Presentation transcript:

HISTORY OF MICROPROCESSORS Gursharan Singh Tatla 1

C ONTENTS  Introduction  4-Bit Microprocessors  8-Bit Microprocessors  16-Bit Microprocessors  32-Bit Microprocessors  64-Bit Microprocessors 2 Gursharan Singh Tatla m

I NTRODUCTION  Fairchild Semiconductors (founded in 1957) invented the first IC in  In 1968, Robert Noyce, Gordan Moore, Andrew Grove resigned from Fairchild Semiconductors.  They founded their own company Intel (Integrated Electronics).  Intel grown from 3 man start-up in 1968 to industrial giant by  It had 20,000 employees and $188 million revenue. 3 Gursharan Singh Tatla m

4- BIT M ICROPROCESSORS 4 Gursharan Singh Tatla m

I NTEL 4004  Introduced in  It was the first microprocessor by Intel.  It was a 4-bit µP.  Its clock speed was 740KHz.  It had 2,300 transistors.  It could execute around 60,000 instructions per second. 5 m Gursharan Singh Tatla

I NTEL 4040  Introduced in  It was also 4-bit µP. 6 m Gursharan Singh Tatla

8- BIT M ICROPROCESSORS 7 Gursharan Singh Tatla m

I NTEL 8008  Introduced in  It was first 8-bit µP.  Its clock speed was 500 KHz.  Could execute 50,000 instructions per second. 8 m Gursharan Singh Tatla

I NTEL 8080  Introduced in  It was also 8-bit µP.  Its clock speed was 2 MHz.  It had 6,000 transistors.  Was 10 times faster than  Could execute 5,00,000 instructions per second. 9 m Gursharan Singh Tatla

I NTEL 8085  Introduced in  It was also 8-bit µP.  Its clock speed was 3 MHz.  Its data bus is 8-bit and address bus is 16-bit.  It had 6,500 transistors.  Could execute 7,69,230 instructions per second.  It could access 64 KB of memory.  It had 246 instructions.  Over 100 million copies were sold m Gursharan Singh Tatla

16- BIT M ICROPROCESSORS 11 Gursharan Singh Tatla m

I NTEL 8086  Introduced in  It was first 16-bit µP.  Its clock speed is 4.77 MHz, 8 MHz and 10 MHz, depending on the version.  Its data bus is 16-bit and address bus is 20-bit.  It had 29,000 transistors.  Could execute 2.5 million instructions per second.  It could access 1 MB of memory.  It had 22,000 instructions.  It had Multiply and Divide instructions m Gursharan Singh Tatla

I NTEL 8088  Introduced in  It was also 16-bit µP.  It was created as a cheaper version of Intel’s  It was a 16-bit processor with an 8-bit external bus.  Could execute 2.5 million instructions per second.  This chip became the most popular in the computer industry when IBM used it for its first PC m Gursharan Singh Tatla

I NTEL &  Introduced in  They were 16-bit µPs.  Clock speed was 6 MHz.  was a cheaper version of with an 8- bit external data bus.  They had additional components like:  Interrupt Controller  Clock Generator  Local Bus Controller  Counters 14 m Gursharan Singh Tatla

I NTEL  Introduced in  It was 16-bit µP.  Its clock speed was 8 MHz.  Its data bus is 16-bit and address bus is 24-bit.  It could address 16 MB of memory.  It had 1,34,000 transistors.  It could execute 4 million instructions per second m Gursharan Singh Tatla

32- BIT M ICROPROCESSORS 16 Gursharan Singh Tatla m

I NTEL  Introduced in  It was first 32-bit µP.  Its data bus is 32-bit and address bus is 32-bit.  It could address 4 GB of memory.  It had 2,75,000 transistors.  Its clock speed varied from 16 MHz to 33 MHz depending upon the various versions.  Different versions:  DX  SX  SL  Intel became the best selling microprocessor in history m Gursharan Singh Tatla

I NTEL  Introduced in  It was also 32-bit µP.  It had 1.2 million transistors.  Its clock speed varied from 16 MHz to 100 MHz depending upon the various versions.  It had five different versions:  DX  SX  DX2  SL  DX4  8 KB of cache memory was introduced m Gursharan Singh Tatla

I NTEL P ENTIUM  Introduced in  It was also 32-bit µP.  It was originally named  Its clock speed was 66 MHz.  Its data bus is 32-bit and address bus is 32-bit.  It could address 4 GB of memory.  Could execute 110 million instructions per second.  Cache memory:  8 KB for instructions.  8 KB for data m Gursharan Singh Tatla

I NTEL P ENTIUM P RO  Introduced in  It was also 32-bit µP.  It had L2 cache of 256 KB.  It had 21 million transistors.  It was primarily used in server systems.  Cache memory:  8 KB for instructions.  8 KB for data.  It had L2 cache of 256 KB m Gursharan Singh Tatla

I NTEL P ENTIUM II  Introduced in  It was also 32-bit µP.  Its clock speed was 233 MHz to 500 MHz.  Could execute 333 million instructions per second.  MMX technology was supported.  L2 cache & processor were on one circuit m Gursharan Singh Tatla

I NTEL P ENTIUM II X EON  Introduced in  It was also 32-bit µP.  It was designed for servers.  Its clock speed was 400 MHz to 450 MHz.  L1 cache of 32 KB & L2 cache of 512 KB, 1MB or 2 MB.  It could work with 4 Xeons in same system m Gursharan Singh Tatla

I NTEL P ENTIUM III  Introduced in  It was also 32-bit µP.  Its clock speed varied from 500 MHz to 1.4 GHz.  It had 9.5 million transistors m Gursharan Singh Tatla

I NTEL P ENTIUM IV  Introduced in  It was also 32-bit µP.  Its clock speed was from 1.3 GHz to 3.8 GHz.  L1 cache was of 32 KB & L2 cache of 256 KB.  It had 42 million transistors.  All internal connections were made from aluminium to copper m Gursharan Singh Tatla

I NTEL D UAL C ORE  Introduced in  It is 32-bit or 64-bit µP.  It has two cores.  Both the cores have there own internal bus and L1 cache, but share the external bus and L2 cache ( Next Slide ).  It supported SMT technology.  SMT: Simultaneously Multi-Threading  E.g.: Adobe Photoshop supported SMT m Gursharan Singh Tatla

26 m Gursharan Singh Tatla

64- BIT M ICROPROCESSORS 27 m Gursharan Singh Tatla

I NTEL C ORE 2  Introduced in  It is a 64-bit µP.  Its clock speed is from 1.2 GHz to 3 GHz.  It has 291 million transistors.  It has 64 KB of L1 cache per core and 4 MB of L2 cache.  It is launched in three different versions:  Intel Core 2 Duo  Intel Core 2 Quad  Intel Core 2 Extreme 28 m Gursharan Singh Tatla

I NTEL C ORE I 7  Introduced in  It is a 64-bit µP.  It has 4 physical cores.  Its clock speed is from 2.66 GHz to 3.33 GHz.  It has 781 million transistors.  It has 64 KB of L1 cache per core, 256 KB of L2 cache and 8 MB of L3 cache m Gursharan Singh Tatla

I NTEL C ORE I 5  Introduced in  It is a 64-bit µP.  It has 4 physical cores.  Its clock speed is from 2.40 GHz to 3.60 GHz.  It has 781 million transistors.  It has 64 KB of L1 cache per core, 256 KB of L2 cache and 8 MB of L3 cache m Gursharan Singh Tatla

I NTEL C ORE I 3  Introduced in  It is a 64-bit µP.  It has 2 physical cores.  Its clock speed is from 2.93 GHz to 3.33 GHz.  It has 781 million transistors.  It has 64 KB of L1 cache per core, 512 KB of L2 cache and 4 MB of L3 cache m Gursharan Singh Tatla

32 m Gursharan Singh Tatla