Lab Environment and Miniproject Assignment Fall 2006 ECE554 Digital Engineering Laboratory Good afternoon everyone. Welcome ECE 554 Digital Engineering laboratory. In this fall 2000 semester, our web page is at www.engr.wisc.edu/ece/courses/ece554.html as shown here.

Lab Environment Ten 2.8 GHz Workstations with 1 GB RAM and 80GB Harddrives Six (may change) 550 MHz Workstations with 512 MB RAM Design Tools HDL Editor, Core Generator System, FPGA Express, Design Manager, Constraints Editor, Modelsim Instrumentation HP8012 Signal Generator – generates system clock Hewlett-Packard Oscilloscopes – probing logic values Agilent Logic Analyzers – monitor data on output pins XSV FPGA Boards See Lab Environment Handout and FAQ page

Lab Warnings Do not wear static electricity generating clothing (wool sweaters) Report stuff dripping from ceiling (don’t touch it). Don’t sit or stand on backs of chairs or lab tables Don’t probe (with oscilloscope) or touch anything on the FPGA board, except for push buttons, DIP switches, and special pins for clocks and expansion headers Do not do any wiring on the board with power on Be sure you download the correct files to the FPGA Carefully read all warnings in Lab Environment handout

XSV FPGA Board Do you have any question so far ? I guess so. I hope it will become clear for you when you start working on the miniproject. Up to this point, we’ve got a configuration bitstream implemented. It’s time to download it to the FPGA. This is done via a PC parallel or printer port.

XSV Board The whole XSV 800 board is outlined as this figure. The Virtex chip is at the center of the board. The main connection to PC is through the parallel port connector. Other than that are stereo audio input/output, VGA output, and so on.

XSV Block Diagram Here is a conceptual diagram of XSV800 board. As I explained earlier, the virtex chip is the heart of this board. The chip is half of the price of this board. That means the whole board costs 1,600 dollars. It’s about the same as a reasonably fast PC computer. So you guys must be careful on doing any experimentation with it.

XSV Board: Features Xilinx Virtex FPGA (Compute) 2 MB Memory (Store for Read/Write) Parallel & Serial Ports to PC (I/O from/to Outside World) Keyboard (PS/2) Port VGA Output to VGA Monitor Audio/Video Converters See XSV Board Manual at: http://homepages.cae.wisc.edu/~ece554 The main features of XSV800 are 1. The 2 MB main memory for storing data 2. The parallel and serial ports for PC interfacing 3. The PS/2 keyboard or mouse port for user interfacing 4. The VGA output to the monitor for displaying graphic and video 5. The audio/video converter for inputting audio or video signal

Current Setup Parallel Cable Serial Cable machine running HyperTerminal Do you have any question so far ? I guess so. I hope it will become clear for you when you start working on the miniproject. Up to this point, we’ve got a configuration bitstream implemented. It’s time to download it to the FPGA. This is done via a PC parallel or printer port. Parallel port: Configuration download Serial port: Miniproject

Miniproject Specification For the miniproject, you will Design a Special Purpose Asynchronous Receiver/Transmitter (SPART) and its testbench in Verilog/VHDL Simulate the design to ensure correct performance Download the design and associated files and demonstrate correction functionality Preparing a report on your design

Miniproject Objectives To get familiar with the lab environment prior to the class project and bench exam To get practice using HDL in your designs To provide the basic I/O interface to the class project To get experience working with a partner To satisfy the previous motivations, ECE 554 is being offered with the following objectives. To deal with problems and solutions associated a large digital system is a worthwhile experience for undergraduate students before going out to the industry. To work effectively in a big group of 5-7 persons is another good opportunity. To use current technology of FPGA for rapid prototyping is unavoiadble in the industry since it is used everywhere. To learn how to use contemporary design tool gives you an edge in getting a better job.

SPART Interface

Processor Interface Data is sent/received across the “bidirectional” data bus Handshaking (status) signals TBR: Transmit Buffer Ready (Empty) RDA: Receive Data Available IOCS: Chip Select IOR/W_: Read or Write Bar signal

SPART Block Diagram

Asynch. Serial Communication Start bit (1 bit wide) Data bits (8 bits) Parity(None, Even, Odd) - optional Stop bit (1 bit wide)

Transmitting Tx must be tested first. Tx shifts the “LSB” out from Tx buffer first. Tx sends “stop bit” when there is nothing to send.

Receiving Receiver samples the RxD to get the beginning of the “start bit” Use “resynchronization” to avoid “metastability” of any flip-flop

Baud Rate Generator

Baudrate and Sampling We want the transmission rate to be constant for different input clocks Baud rates of 4800 and 9600 bit per second Sampling rate = x16 of the baud rate (bit rate) Divide the clock (5 and 20 MHz) to get the “Enable” signal (sampling rate)

Testbench (Mock Processor) A finite state machine Receive data on the RxD from keyboard and transmit (echos) back on the TxD back to the HyperTerminal Load Baud Rate Generator with Arbitrary value Demonstrate ability to work with different clocks and BRG divisor values Note that it is not provided.

Demonstration Demos done in lab on 9/25 and 9/26 at start of class.

Report Due 9/25 and 9/26 Verilog/VHDL code for your design with clear comments Description of the function of the SPART and each block in the design, including the testbench Record of experiments conducted and how the design was tested Problems encountered and solutions employed