8254 - Programmable Interval Timer This is a bus compatible digital timer / counter. Usage real time clock, event counter, a digital one shot, a square wave generator, a complex wave form generator.

Pinout and block diagram

Modes of function Each of the three counters can be programmed as : Timer Generate a required time delay to the accuracy of one clock period, Generate an one shot pulse (retriggerable or non- retriggerable). Counter Count the number of events occurred on its input terminal during unit time, Divide the input clock by any number.

I/O pin description Each timer contains: a CLK input which provides the basic operating frequency to the timer a gate input pin which controls the timer in some modes an output (OUT) connection to obtain the output of the timer

Working principle 8254 possesses three independent binary down counters 16 bits wide: A counter is loaded with a number proportional to required time delay, The time required to empty the counter is the delay time, The time delay is programmable, delay can be changed with instructions, Single or repetitive time delay can be generated. A count can be read by MPU while the counter is decrementing,

8254: Mode of operations

Mode 0: Interrupt on terminal count The output becomes a logic 0 when the control word is written and remains there until N plus the number of programmed counts

Mode 1- HW triggered / programmable one shot. The triggering must be done through the GATE input by sending a 0-to-1 pulse to it. Steps: load the count register a 0-to-1 pulse must be sent to the GATE input to trigger the count. after sending the 0-to-1 pulse to GATE, OUT becomes low and stays low for a duration of N*T, then becomes high and stays high until the GATE is triggered again. If during the activation, a retriggered happened, then restart the down counting.

Mode 1 (cont.)

Mode 2: Rate Generator (Divide-by-N counter If GATE=1, OUT will be high for N*T, goes low only for one clock pulse, then counter is reloaded automatically, The cycle is repeated until reprogrammed or Gate pin set to 0.

Mode 3: Square wave rate generator Generates a continuous square-wave with G set to 1. If count is even, 50% duty cycle otherwise OUT is high 1 cycle longer

Mode 4: Software triggered strobe If GATE=1, the output will go high when loading the count, it will stay high for duration N*T. After the count reaches zero, it becomes low for one clock pulse, then goes high again and stays high until a new command word or new count is loaded To repeat the strobe, the count must be reloaded

Mode 5: Hardware triggered strobe Similar to Mode4, except that the triggering must be done with the GATE input The count starts only when a 0-to-1 pulse is sent to the GATE input If GATE retriggered during the counting, it will restart the down counting

8254: Addresses of internal registers

8254: Format of the control word

8254: Steps of program codes Write the control word to configure the 8254 into the control register Write the low order byte of count into a counter register Write the higher order byte of count into a counter register The corresponding Gate input must be high to start down counting.

8254: Steps of read value of the count Write the control word to latch a count in the output latch into the control register, Perform two I/O read operations

Example #1: Write the instructions to configure the counter # 2 of 8254 as counter (mode 0) ? Given Chip select is enabled when address line A7 = 1, Address lines A1 and A0 are connected to the A1 and A0 pins of 8254, The 8254 chip is I/O mapped, The address of counter # 2 is 82H The address of control register is 83H

Example #1: (cont.) Control words Control word to initialize the counter # 2 in mode 0 is B0h Control word for latching (bits D5 and D4 equal to 0) is 80h

Example #1: (cont.) Instructions: COUNTER: MVIA, B0h ; control word to initialize counter # 2 OUT 83h ; Write in the control register MVIA, COUNT_LOBYTE ; Low order byte of the count OUT 82h ;Load counter#2 with low order byte of the count MVIA, COUNT_HIBYTE ; High order byte of the count OUT 82h ;Load counter#2 with high order byte of the count READ: MVIA, 80h ; control word to latch a count IN 82h ; read low order byte MOV D, A ; store low order byte in reg. D IN 82h ; read high order byte ORA D ; OR low and high order bytes to set Z flag JNZ READ : if the counter is not 0 go back to read next count.

Mode 3: Square Wave Generator Description A continuous square wave is generated whose period is equal to the count. When a count is loaded, the OUT pin is high, The count is decremented by 2 at every clock cycle, When the count reaches zero, the OUT pin goes low, The count is reloaded again.

Example: Configure the counter # 1 as 1KHz square wave generator (mode 3) Given Chip select is enabled when address line A7=1, Address lines A1 and A0 are connected to the A1 and A0 pins of 8254, The 8254 chip is I/O mapped, The clock frequency is 2MHz (0.5μs clock period)

Solution From the address table determine The address of counter # 1 is 81H The address of control register is 83H Determine the count The count is calculated by dividing clock frequency by the square wave frequency 2MHz /1KHz =2000 = 07D0h.

Solution (cont.) From the bit pattern format determine Control word to initialize counter # 1 in mode 0 is 76h

Solution (cont.) Instructions: SQWAVE: MVIA, 76h ; control word mode3 and counter # 1 OUT 83h ; Write in the control register MVIA, D0h ; Low order byte of the count OUT 81h ; Load counter#1 with low order byte of the count MVIA, 07h ; High order byte of the count OUT 81h ; Load counter#1 with high order byte of the count HLT