Chap 7. Register Transfers and Datapaths

7.1 Datapaths and Operations use a modular approach a digital system is a sequential circuit but, difficult to specify a large digital system with state table (number of states is too large)  modular and hierarchical approach each module performs some functional task & consists of digital devices as registers, counters, decoders, multiplexers, control logic....

7.1 Datapaths and Operations partition a digital system into two types of modules: datapath :- perform data-processing operations control unit :- determines the sequence of those operations control signals binary signals that activate the various data-processing operations

7.1 Datapaths and Operations digital modules are best defined by the registers & operations example of register operations: shift, count, clear & load registers are the basic component of the digital system information flow and processing task on data: register transfer basic component of register transfer operations 1. set of registers 2. operations that are performed on the data in registers 3. control that supervises the sequence of operations Register perform one or more elementary operations such as load, count, add, subtract, & shift a counter: a register that increments a number by one

7.1 Datapaths and Operations microoperations elementary operations performed on the data in registers examples loading the contents of one register into another adding the contents of 2 registers & incrementing the contents of a register usually performed in parallel during one clock-pulse period the control unit provides signals that sequence the microoperations in a prescribed manner the results may determine both the sequence of control signals & the sequence of future microoperations to be executed

7.2 Register Transfer Operations designated by capital letters (may followed by numerals) (ex) PC, IR, R1, R2 flip-flops in an n-bit register are numbered in sequence from 0 to n-1

7.2 Register Transfer Operations information transfer is designated by a replacement operator R2  R1: a transfer of the contents of R1 (source) into R2 (destination) don't want the transfer to occur with every clock pulse, but only under a predetermined condition  conditional statement If ( K1 = 1 ) then ( R2  R1 ) or K1 : R2  R1

7.3 Microoperations an elementary operation performed with the data stored in registers 4 categories: 1) Transfer microoperations 2) Arithmetic microoperations 3) Logic microoperations 4) Shift microoperations

7.3 Microoperations Arithmetic Microoperations basic: add, subtract, increment, decrement, & complement add: R0  R1 + R2 subtract: R0  R1 + R2' + 1 (instead of R0  R1 - R2) increment & decrement: plus-one & minus-one operation multiplication (*) & division (/) are not included in basic operations implemented by a special combinational circuit

7.3 Microoperations X' K1 : R1  R1 + R2 X K1 : R1  R1 + R2' + 1 timing variable K1 activates an operation to add or subtract control variable X determines the operation the output is loaded into R1 on any positive clock edge X' K1 + X K1 = (X' + X) K1 = K1 X selects the operation & K1 loads the result into R1

7.3 Microoperations Logic Microoperations useful for manipulating the bits stored in a register consider each bit in the register separately & treat it as a binary variable

7.3 Microoperations NOT (bar(-) or ', same as 1's complement) AND (), OR () (ex) K1+K2: R1  R2+R3, R4  R5  R6 (or) (add) (or) Logic Arithmetic Logic easily implemented with a group of gates can change bit values, clear a group of bits, or insert new bit values in a register

7.3 Microoperations 1 0101 101 1010 1011 R1 00000000 11 11 1111 R2 00000000 1010 1011 R1  R1  R2 masking out delete all 1's from a selected portion of a register 10101101 1 0101 011 R1 11 111111 00000000 R2 11 111111 1 0101 011 R1  R1  R2 10101101 1 010 101 1 R1 1111 111 1 00000000 R2 01010010 1 010 101 1 R1  R1  R2

7.3 Microoperations Shift Microoperations used for lateral movement of data used in serial transfer of data also used for manipulating contents of registers in arithmetic, logic and control operations (logical) shift R0  sr R0, R1  sl R2 incoming bit :- assuming 0 outgoing bit :- discarded

7.4 Multiplexer-Based Transfer a register receives data from two or more different sources If(K1=1) then (R0 R1) else if(K2=1) then (R0  R2) control conditions: K1=1: R0  R1, K1’ K2: R0  R2

7.5 Bus-Based Transfer digital computer has many registers and paths to transfer data a bus system: a more efficient scheme for transferring data between registers in a multiple register configuration control signals select a source register & destination register(s)

7.5 Bus-Based Transfer Dedicated multiplexers 3 n-bit 2-to-1 multiplexers, each with its own select signal 3 registers, each with its own load signal 2n AND & n OR gates per multiplexer (total 9n gates) Single bus 3-to-1 multiplexer and parallel load registers Select (control inputs) determines the contents of the source 3n AND & n OR gates (total 4n gates) (ex) R2  R1 control variables must select register R0 as the source, & register R2 as the destination

7.5 Bus-Based Transfer Three-State Bus a bus system can be constructed with three-state buffers (instead of multiplexers) form a bit line of bus, & bus is implemented using only one level of logic gates signals can travel in two directions on a three-state bus

7.5 Bus-Based Transfer three-state buffers are enabled  lines are output three-state buffers are disabled  lines are input a bidirectional bus system transfer information in both directions constructed with three-state buffers to control the direction of info flow in the bus multiplexer-implemented bus has 6 data connections three-state bus has 3 data connections

7.5 Bus-Based Transfer Memory Transfer a memory word is symbolized by the letter M Read: DR  M[AR] (DR: data register, AR: address register) Write: M[AR]  DR

7.5 Bus-Based Transfer case study: memory unit write operation: M[A1]  D2 required select input 01 (A1) select input for data bus source 10 (D2) select input for data bus destination 11 (Memory Write) read operation: D1  M[A2] select input for address decoder 10 (A2) select input for data bus source 11 (Memory Read) select input for data bus destination 01 (D1)

7.6 Datapaths a central component in a digital computer system combination of a set of registers with a shared ALU and interconnecting paths the processor part of the computer is referred to as data path (because it forms the paths for the operations among registers) (cf) control path simple bus-based datapath with 4 registers, an ALU & a shifter

7.6 Datapaths the most efficient way to connect a large number of registers  common buses registers interact by a direct transfer of data, as well as perform various microoperations each register is connected to two sets of multiplexers to form input buses A and B selection inputs select one register for the corresponding bus A & B buses are applied to the inputs of a common ALU select inputs of the ALU determine the particular operation destination register is selected by a decoder a number of status bits in ALU useful for checking certain relationships after ALU operation carry C, overflow V, zero status Z, sign status S

7.6 Datapaths arithmetic/logic microoperations: ALU (G select) shift microoperations: shifter (H select) (ex) R1  R2 + R3 1. A select: contents of R2 onto bus A 2. B select: contents of R3 onto bus B 3. G select: ALU operation A + B 4. MF select: ALU output to MUX F output 5. MD select: MUX F output onto bus D 6. destination select: select R1 7. load enable of R1

7.7 Arithmetic Logic Unit (ALU) ALU is a combinational circuit that performs a set of basic arithmetic & logic microoperations

7.7 Arithmetic Logic Unit (ALU) a typical 4-bit ALU 4 data inputs from A & B, and 4 data outputs to F mode select input S2 distinguishes between arithmetic & logic operations 2 function select inputs S1 & S0 specify the particular operations possible to specify 4 arithmetic & 4 logic operations input & output carries have meaning only during an arithmetic operation input carry Cin is used as a 4th selection variable for arithmetic ops three stages in the design of a typical ALU 1) design of arithmetic section 2) design of logic section 3) combined to form the ALU

7.7 Arithmetic Logic Unit (ALU) Arithmetic Circuit basic component of an arithmetic circuit is "Parallel Adder" G = X + Y + Cin X: the n-bit binary number at the A inputs Y: the n-bit binary number at the B inputs Cin: input carry

7.7 Arithmetic Logic Unit (ALU) 2 select lines S1 & S0 obtain a variety of arithmetic operations the combinational circuit can be implemented with n muxs 0, Bi, Bi', & 1

7.7 Arithmetic Logic Unit (ALU) simplified in the map; Y = Bi S0 + Bi' S1

7.7 Arithmetic Logic Unit (ALU) Logic Circuit logic microoperations manipulate bits of the operands by treating each bit in a register as a binary variable 4 basic operaitons: AND, OR, XOR, & complement

7.7 Arithmetic Logic Unit (ALU) ALU = arithmetic circuit + logic circuit one stage of ALU repeat n times for an n-bit ALU

7.7 Arithmetic Logic Unit (ALU) provide 8 arithmetic & 4 logic operations

7.8 The Shifter shift the value on Bus A, placing the result on an input of MUX F provide the shift operations not available in ALU (right shift & left shift) a bidirectional shift register with parallel load a clock pulse loads the output of Bus A into the shift register 2nd clock pulse performs the shift & 3rd clock pulse transfers the data to the selected destination can be done in one clock pulse in combinational circuits

7.8 The Shifter selection variable S S=0, right shift (IR: serial input) S=1, left shift (IL: serial input) to shift an operand by M>1 bit positions, perform m 1-bit position shifts taking m clock cycles

7.8 The Shifter Barrel Shifter data are shifted more than once during a single operation shift input data bits by a number of positions a cyclic rotation consist of 4 multiplexers w/ 2 common selection lines S1 & S0 a barrel shifter w/ 2n input & output lines requires 2n multiplexers, each having 2n data inputs and n selection inputs

7.9 Datapath Representation

7.9 Datapath Representation

7.10 The Control Word the selection variable control the microoperations executed within the unit for any given clock pulse selection variables control the buses, the ALU, the shifter, & the destination register

7.10 The Control Word a register file of seven registers R1 through R7; outputs go through two sets of multiplexers to select input to ALU input data from an external source are selected by the same muxs; the output of ALU goes through a shifter & into output bus; the output from the shifter is transferred to any one of the registers & can also be directed to an external destination ALU provides the binary data for the four status bits: C, Z, S, V there are 16 binary selection inputs in the unit & their control words is defined as follows: 3 bits in DA: select a destination register; 3 bits in AA & BA: select source registers for input of ALU; 1 bit in MB: register or constant; 5 bits in FS: select one of 14 operations in ALU; 1 bit in MD: function unit output or the data on DATA 1 bits in RW: select register is written or not;  17-bit control word specifies a particular microoperation

7.10 The Control Word specified functions functions of all selection variables

7.10 The Control Word (ex1) R1  R2 + R3' + 1 - DA: R1 001 - AA: R2 010 - BA: R3 011 ==> 001 010 011 0 00101 0 1 - MB: register 0 - FS: A+B'+1 00101 - MD: Function 0 - RW: Write 1 (ex2) R4  sr R6 - DA: R4 100 - AA: R6 110 - BA: - 000 ==> 100 110 000 0 10001 0 1 - MB: register 0 - FS: sl A 10001 - MD: Function 0 - RW: Write 1

7.10 The Control Word

7.10 The Control Word many microoperations can be generated in the processor unit most efficient way to generate control words:  store them in memory unit  control memory  microprogramming (Chap 8) by reading consecutive control words from memory