CPPM ATLAS Pixel upgrade pour HL LHC LPNHE, Paris 10 octobre 2012 A.Rozanov Paris-LPNHE 10.10.12 ATLAS pixel
IBL construction and installation 2013-2014 Paris-LPNHE 10.10.12 ATLAS pixel
IBL Stave-0 final qualification Stave=0 have been thermally qualified and is under Thermal and pressure cycles Stave TFOM is bellow 17°C cm2/W which is acceptable and within expected values Power up to 345W on a stave and system permit to maintain the sensor to -15°C which is a good input to prevent thermal runaway Stave fully loaded with modules A-side C-side C-side Paris-LPNHE 10.10.12 ATLAS pixel
Cooling line prototyping Induction Brazing qualification for PP0 joint is ongoing Quality still OK, 40 sample brazed and tested: He leaks, visual, thermal shock Stave extension tests in October June 2013: 14 staves should be assembled and having all components in hand for 14 staves commissioning. Sealing of the IBL volume for cold tests. Brazed joint metallurgical analysis Induction Chamber PP1 Electrical Break PP0 Ti Sleeve PP1 Ti Fitting Paris-LPNHE 10.10.12 ATLAS pixel
Paris-LPNHE 10.10.12 ATLAS pixel LoI pixel layout Layout classique – Cylindres barrel et disques CS IN2P3 21 Juin 2012 First LoI-phase-II: présentation à AW, Montreux, Octobre 12 Final LoI phase-II: Janvier 2013 Paris-LPNHE 10.10.12 ATLAS pixel
Inner Pixels Tuned to Inner pixels R=4 cm and R=8 cm Option: Two IBL-like barrel layers Tuned to Inner pixels R=4 cm and R=8 cm Compatible with clamp shell installation 0.55%X0 Bare stave + 0.03%X0 support = 0.58% X0 A.Rozanov Montreux 2.10.2012
Material per layer Component IBL-like X0% Sensor 150um 0.16 FE chip 100um 0.11 Flex 0.19 Cables 0.29 Glue 0.03 IBL like bare stave 0.55 Support Total 1.36 Stave type X0 Current pixel 3.8% IBL 1.7% ITK IBL-like 1.36% ITK I-beam 1.21% A.Rozanov Montreux 2.10.2012
Inner Pixels Front End FE-electronics with classical sensors, two main options: 65 nm pixel 25x150 µm 3D 130nm pixel 50x125 µm HV CMOS monolithic sensor+electronics 180nm HV2FEI4 ATLAS chip with capacitive coupling to FEI4 subpixel 33x125 µm More RD on different combinations of HV-HR CMOS, 65 nm, 3D Test of 65nm chip at CERN PS, excellent results for SEU tolerance, some concern on total dose in shift registers 65 nm prototype A.Rozanov Montreux 2.10.2012 65 nm test pixel matrix
Inner Pixels FE-electronics: 3D 130nm pixel 50x125 µm A.Rozanov Montreux 2.10.2012 HV2FEI4 demontrator
Inner Pixels Analog tier Thr=2200e Sthr=150e noise=46e - 3D FE-electronics: FE-TC4-P1 test chip pixel 50x166 µm show good results Analog tier Thr=2200e Sthr=150e noise=46e - Digital tier Sthr=174e noise=42e - A.Rozanov Montreux 2.10.2012
Inner Pixels HV CMOS monolithic sensor+electronics 180nm HV2FEI4 ATLAS chip with capacitive coupling to FEI4 subpixel 33x125 µm A.Rozanov Montreux 2.10.2012 Before irradiation HV2FEI4 demonstrator
HV2FEI4 reached already 375 MRads Despite degradations at high temperature (42 degC) chip is working Next round of cold tests at CERN PS at -10 deg C New more Rad Hard chip in November 2012 Paris-LPNHE 10.10.12 ATLAS pixel
IBL and outer ITK pixels FE-I4 Test of FE-I4-B SEU - confirms good resistance as expected Test of General ADC – works up to 375 Mrads Test of temperature sensor inside FE-I4-B – calibrate as a function of the dose Paris-LPNHE 10.10.12 ATLAS pixel
Paris-LPNHE 10.10.12 ATLAS pixel ATLAS pixel upgrade pour HL LHC Responsabilités: Positionnement du CPPM A.Rozanov - chair Joint Pixel-IBL-IB, ITK-SC A.Rozanov - editor Pixel/Readout ITK LoI Phase-II E.Vigeolas - responsable stave IBL, SC E.Vigeolas - ITK local support group, backup document local support Lol Phase-II J.C.Clémens - coordination électronique 3D IN2P3 G.Hallewell - coordination group sonar ID M.Barbero - programme TALENT au CPPM Paris-LPNHE 10.10.12 ATLAS pixel
Paris-LPNHE 10.10.12 ATLAS pixel CPPM: Management Plan de management: Responsabilités Stave IBL, Local support ITK - E.Vigeolas Sonar – Cooling - G.Hallewell Electronique, via last AIDA -J.C. Clémens FE-I4 - M.Menouni FE-TC4 - P.Pangaud 65 nm - M.Menouni HV-HR CMOS - P.Pangaud Stave -1 Wire Bonding Paris-LPNHE 10.10.12 ATLAS pixel
CPPM: Ressources humaines Tâches Nom Corps Service 3D J.C.Clemens IR Inst IBL stave, ITK E.Vigeolas Mec Tests FE-I4, TC4, 65nm etc P.Breugnon Elec FE-I4, 65 nm M.Menouni 3D,HVCMOS,65nm P.Pangaud HVCMOS, 65 nm S.Godiot FE-I4, C4-P3, 65 nm D.Fougeron IE FE-I4 , 65 nm F.Gensolen Test 3D, HVCMOS F.Bompard Vitesse F.Rivière AI 65nm SEU test M.Jevaud Sonar, cooling G.Hallewel Paris-LPNHE 10.10.12 ATLAS pixel
Paris-LPNHE 10.10.12 ATLAS pixel CPPM: Budget Origine Budget alloué 2012 Dépenses engagées 2012 Demande 2013 Fonctionnement et petits équipements IN2P3 2000 1600 12500 Personnel, missions, fonctionnement, ANR ANR Vitesse 56601 39107 Jan-Dec 2012 17500 Jan-Avr 2013 Frédéric Bompard 25000 via LAL MPW run Sous-traitance et matières 57000 11000 Mécanique/Cooling 8900 Electronique 10000 Elec+mécanique CERN 9000 Ti tube Octobre 15000 HV2FEI4-2 Novembre 4000 Carte PCB-HV Octobre 3000 Soudure Ti Oct-Dec 2000 Sonar (CO2) Oct-Dec 115000 Paris-LPNHE 10.10.12 ATLAS pixel
Paris-LPNHE 10.10.12 ATLAS pixel Phase0 en 2013 Assemblage/test IBL 6000 Fonctionnement Pixel+IBL 4000 Upgrade sonar (thermosiphon, FPGA, CO2) 2500 Total 12500 Paris-LPNHE 10.10.12 ATLAS pixel
Mechanique/cooling PhaseI-II en 2013 Proto tubes 7000 Assemblage staves IVW 19000 Test thermique CO2 4000 Total 30000 Paris-LPNHE 10.10.12 ATLAS pixel
RD electronique PhaseI-II en 2013 FE-I4-B Interface USBpix 3000 Chip test FE-I4-C 2x2mm 130nm 14000 PCB FE-I4-C 4000 PC banc de test FE-I4 1500 HVCMOS run AMS 180nm 15000 HVCMOS run GF 130 nm Flip-chip tests HV2FEI4 5000 PCB et DAQ HVCMOS 2000 PC HVCMOS Run 65 nm 20000 Licence Cliosoft PCB 65nm Total 85000 Paris-LPNHE 10.10.12 ATLAS pixel
Paris-LPNHE 10.10.12 ATLAS pixel Conclusions Faits marquants Grand succès de FE-I4-A/B – le plus grand chip hybride HEP au monde Excellente qualité du tier analogique aminci à 10 µm, cross talks entre deux tiers en électronique 3D Communication entre tier analogique et digital FE-TC4-P1 (tous les pixels connectés) IBL sur le planning accéléré de 2 ans HV2FEI4 fonctionnel et communique avec FE-I4 HV2FEI4 détecte des particules sur la sortie ampli même après 375 MRads Paris-LPNHE 10.10.12 ATLAS pixel
Paris-LPNHE 10.10.12 ATLAS pixel Spare Paris-LPNHE 10.10.12 ATLAS pixel
Last qualifications steps The final stave design have been thermally qualified and is under Thermal and pressure cycles Stave TFOM is bellow 17°C cm2/W which is acceptable and within expected values Power up to 345W on a stave and system permit to maintain the sensor to -15°C which is a good input to prevent thermal runaway Paris-LPNHE 10.10.12 ATLAS pixel
Chip électronique FE-I4 CPPM FE-I4 conçu pour l'IBL pour grands taux d'occupation et de résistance aux radiations Pixels de 250 * 50 µm Techno IBM 130 nm, testée jusqu'à 400 MRads FE-I4-A – record de taille HEP: 80 columns×336 rows = 26880 pixels/FE, 20x19 mm , 87 M transistors FE-I4-B -- retour décembre 2011, premiers tests très positifs- Contributions design ASIC CPPM: Registres de configuration (local et global) Discriminateur basse consommation Capteur de température ADC (lecture alims, courant de fuite, température etc) Multiplexeur analogique Buffers de lecture des signaux analogiques Générateur de calibration Amplificateur opérationnel multi-usage Cooperation IN2P3: Daniel Dzahini (Grenoble) Renaud Gaglione (Annecy) Julien Fleury (LAL) Paris-LPNHE 10.10.12 ATLAS pixel
Paris-LPNHE 10.10.12 ATLAS pixel FE électronique FE-I4 CPPM Caractérisation et test SEU des registres avec le faisceau de protons PS CERN 5.5 1011 protons/spill Paris-LPNHE 10.10.12 ATLAS pixel Mémoire SEU CPPM
Paris-LPNHE 10.10.12 ATLAS pixel Test of first 3D wafers Two wafers de 3D assemblies arrived CPPM September 2011. Third wafer was diced into chips. Problems with uniformity of the thinning of the upper tier: 15-20% of the wafer surface is defective. Measurements of the resistance of daisy chains and power pads have shown the short circuits between copper surface contacts between two tiers. Few chips without shorts selected. They works, but no communication between tiers established. Problem identified by Tezzaron to be bad wafer alignment at new production facility at Tempe(AZ). The same alignment problem probably creates weak adhesion and non-uniformities during thinning. Next batch of wafers will bonds at facility at Austria in November 2011 with final delivery in spring 2012. Paris-LPNHE 10.10.12 ATLAS pixel
Performance of analog tier from 3D wafer with 10 µm thickness Excellent performance of the analog tier with 10 µm thickness. Paris-LPNHE 10.10.12 ATLAS pixel
FE-TC4-DS simple digital tier 11 “DRUM” cells (noise generator) “DRUM” cell structure: Digital input (test) or Tier1 output Read-out shift register (1b) Test Shielding strategy : Tested at CPPM lab 5 columns without any shielding (reference), 4 columns with shielding in metal 5, 2 columns with shielding in metal 3, 2 columns with both shielding. Paris-LPNHE 10.10.12 ATLAS pixel
Noise and threshold maps after DRUM activated Mapping of threshold no DRUM activated Mapping of threshold with DRUM activated No DRUM ACTIVATED Mapping of noise no DRUM activated DRUM ACTIVATED Mapping of noise with DRUM activated Paris-LPNHE 10.10.12 ATLAS pixel
CPPM ATLAS Pixel Upgrade Mécanique-Refroidissement CPPM: Management Plan de management: Organigramme projet labo Responsabilités CPPM ATLAS Pixel Upgrade Mécanique-Refroidissement Electronique Stave IBL Sonar Cooling FE-I4 3D 65 nm HV–HR CMOS ITK support GF Tezzaron AMS 180nm GF 130nm A-B C vialast Paris-LPNHE 10.10.12 ATLAS pixel