Introduction to Logic Design Alan Marcovitz

Chapter 1: Introduction Adapted from Alan Marcovitz’s Introduction to Logic and Computer Design

Digital Signals Digital Signals have two basic states: 1 (logic “high”, or H, or “on”) 0 (logic “low”, or L, or “off”) Digital values are in a binary format. Binary means 2 states. A good example of binary is a light (only on or off)

Binary In Binary, there are only 0’s and 1’s. These numbers are called “Base-2” ( Example: 0102) Base 2 = Base 10 000 = 0 001 = 1 010 = 2 011 = 3 100 = 4 101 = 5 110 = 6 111 = 7 We count in “Base-10” (0 to 9) Binary to Decimal

Binary as a Voltage Voltages are used to represent logic values: A voltage present (called Vcc or Vdd) = 1 Zero Volts or ground (called gnd or Vss) = 0 A simple switch can provide a logic high or a logic low.

A Simple Switch Here is a simple switch used to provide a logic value: Vcc Vcc, or 1 Vcc Gnd, or 0 There are other ways to connect a switch.

Converting to decimal from binary: Example Number systems Converting to decimal from binary: Evaluate the power series Example 5 4 3 2 1 1 0 1 1 1 12 1*25 0*24 1*23 1*22 + + + + 1*21 1*20 4710 + =

Convert to decimal from binary: Number systems Convert to decimal from binary: 1011011 27 91 109 -109 551

Review of Number systems Memorize the first ten powers of two

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Number systems Converting to binary from decimal: Divide the decimal number by 2 repeatedly. The remainder gives the digits of the binary number 2 746 2 373 R 0 10111010102 2 186 R 1 2 93 R 0 2 46 R 1 2 23 R 0 2 11 R 1 2 5 R 1 2 2 R 1 2 1 R 0

Number systems 65 Convert to binary from decimal: 110101 101110 100001 100000 1000001

Hexadecimals – Base 16 Shorthand for binary Binary digits are grouped into 4 Start at the least significant If number of digits is not a multiple of 4, add zeros Each group is interpreted in decimal Digits above 9 are represented by the first six letter of the alphabet: 10: A; 11: B; 12: C; 13: D; 14: E; 15: F Example: 10111010102 = 0010 1110 10102 = 2EA16

Number systems 1111111 Convert to hexadecimal from binary: 771 177 F7 127

Converting to decimal from hex: Example Hexadecimals – Base 16 Converting to decimal from hex: Evaluate the power series Example 2 1 2 E A 16 2*162 14*161 10*160 + + 74610 =

Number systems 65 Convert to decimal from hexadecimal: 101 86 100001 41

Octals – Base 8 Same steps as for conversion as binary and hexadecimal and any other base Converting to octal from decimal: Divide the decimal number by 8 repeatedly. The remainder gives the digits of the binary number Example: Convert 15310 to base 8.

Number systems Convert to octal from decimal: 15 71 177 F7 17 27

Converting to decimal from hex: Example Octals – Base 16 Converting to decimal from hex: Evaluate the power series Example 2 1 2 0 7 8 2*82 0*81 7*160 + + 13510 =

Binary Addition Add one digit at a time Obtain a sum and a carry Similar to decimal addition – but pay attention to the base

Binary Addition Add the following binary number 10011+11111 110010 001100 101110 021120 010011

Binary Addition Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

Binary Addition Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

Signed Numbers Signed numbers are mostly stored in two’s complements form Leading bit is 0 for positive numbers and 1 for negative For n bits, the range of numbers that can be stored is: -2n-1: 2n-1-1 To derive the binary negative (two’s complement) of a number: Determine the magnitude (how many bits) Find the binary equivalent of the magnitude Complement each bit Add 1

Signed Numbers Example: Derive the 6-bit binary negative (two’s complement) of 17 Determine the magnitude (how many bits) 6bits Find the binary equivalent of the magnitude 010001 Complement each bit 101110 Add 1 101111

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Signed Numbers Derive the 5-bit binary negative (two’s complement) of 17 0101111 101111 10000 01111 01110 No answer

Overflow This occurs when the sum is out of range Example: for 4-bit numbers, the range is [- 8:7] Find the sum of +4 and +5 Find the sum of -4 and -5 Addition of two numbers of the opposite sign never produces overflow Adding two same-signed numbers and obtaining a result of the opposite sign indicates overflow

Overflow For each of the following problems, enter A if the result is an overflow and B if it’s not. Assume the number of bits is 6 15 + 17 -15 + 17 -15 -17 2 - 3

Binary Subtraction Take the two complement of the second operand Then add For signed numbers: Ignore the carry-out of the higher order If two numbers of the same sign are added, and a result of the opposite sign is obtained, there’s an overflow Ex: 7 – 5; -7 – 5 For Unsigned number A carry-out of zero in the higher-order bit indicates overflow Ex: 5 - 7

Binary Subtraction What is the 5-bit binary representation of 8 -15 10111 11000 01001 11001 overflow D

Example Fractions . 1 0 1 2 1*2-1 0*2-2 1*2-3 .62510 Converting fractions to decimal from binary: Example . 1 0 1 2 1*2-1 0*2-2 1*2-3 + + .62510 =

Fractions Convert .01112 to decimal .875 .375 .4375 .0700 4.375 C

Fractions Converting to binary from decimal: Multiply the decimal number by 2 repeatedly. Use the integer part as the next digit each time, and then discard the integer When the fraction part is zero, we have an exact conversion Add trailing zeros to obtain the desired size For some fractions, we never get an exact conversion because the fraction parts repeats, example: .3 .625*2 = 1.25 .1 .25*2 = 0.50 .10 .5*2 = 1.00 .101

Examples Convert the following to base 2 : .7510 .111000 .000011 .110000 .111111 .101000 C

Mixed Numbers Covert the integer and the fraction separately Example: 5.75 = 101.11

Examples Convert the following to base 10 : 11.011002 3.7500 3.0300 3.1875 3.3750 E

Other Codes Example: Gray Code Only one bit changes at a time 000,001,011,010,110,111,101,100 Why is this useful? To avoid intermediate hardware errors Actually there’s a family of Gray codes Ref: http://lib-www.lanl.gov/numerical/bookcpdf/c20-2.pdf

ASCII - Character Codes Stands for American Standard Code for Information Interchange Only 7 bits defined

ASCII table

Examples Convert the following Alphanumeric character to ASCII - & 010 0110 000001010 0110010 000001

Error Detection - Even Parity Sometimes high-order bit of ASCII coded to enable detection of errors Even parity – set bit to make number of 1’s even If the number of 1’s is not even at the receiving end, then there’s an error somewhere. The next step depends on the application Ex: receiver could assume it was a random error and send an ASCII NAK (negative acknowledge) signal to have the message resent. Examples A (01000001) with even parity is 01000001 C (01000011) with even parity is 11000011

Odd Parity Similar except make the number of 1’s odd Examples A (01000001) with odd parity is 11000001 C (01000011) with odd parity is 01000011

Error Detection Note that parity detects only simple errors One, three, etc. bits More complex methods exist Some that enable recovery of original info Cost is more redundant bits

Logic Gates Basic Digital logic is based on 3 primary functions (the basic gates): AND OR NOT

The AND function The AND function: If all the inputs are high is the output is high If any input is low, the output is low “If this input AND this input are high, the output is high”

AND Logic Symbol Inputs Output If both inputs are 1, the output is 1 If any input is 0, the output is 0

AND Logic Symbol Output Inputs Determine the output

AND Logic Symbol Output Inputs 1 Determine the output

AND Logic Symbol 1 1 Output Inputs 1 Determine the output

AND Truth Table Input Output 1 To help understand the function of a digital device, a Truth Table is used: Input Output 1 Every possible input combination AND Function

AND Gates It is possible to have AND gates with more than 2 inputs. The same logic rules apply – “if any input…”

The OR function The OR function: if any input is high, the output is high if all inputs are low, the output is low “If this input OR this input is high, the output is high”

OR Logic Symbol Inputs Output If any input is 1, the output is 1 If all inputs are 0, the output is 0

OR Logic Symbol Inputs Output Determine the output

OR Logic Symbol Inputs 1 Output 1 Determine the output

OR Logic Symbol Output 1 1 Inputs 1 Determine the output

OR Truth Table Truth Table Input Output 1 OR Function

The NOT function The NOT function: If any input is high, the output is low If any input is low, the output is high “The output is the opposite state of the input” The NOT function is often called INVERTER

NOT Logic Symbol Input Output If the input is 1, the output is 0

NOT Logic Symbol Input Output 1 Determine the output

NOT Logic Symbol Output Input 1 Determine the output

Summary OR (written as +)1 a + b (read a OR b) is 1 if and only if a = 1 or b = 1 or both AND (written as  or simply two variables catenated) a  b = ab (read a AND b) is 1 if and only if a = 1 and b = 1. NOT (written) a (read NOT a) is 1 if and only if a = 0

Chapter 2: Combinational Systems Adapted from Alan Marcovitz’s Introduction to Logic and Computer Design

Riddle Four switches can be turned on or off. One is the switch for the incandescent overhead light in the next room, which is initially off, but you don't know which. The other three switches do nothing. From the room with the switches in it, you can't see whether the light in the next room is turned on or off. You may flip the switches as often and as many times as you like, but once you enter the next room to check on the light, you must be able to say which switch controls the light without flipping the switches any further. (And you can't open the door without entering, either!) How can you determine which switch controls the light?

Design Process for Combinational Systems Begins with a verbal description of the intended system, known as the PROBLEM STATEMENT A block diagram of the system should be developed The desired objectives and constraints

Illustrations A system with four inputs, A, B, C, and D, and one output, Z, such that Z = 1 iff three of the inputs are 1. A single light (that can be on or off) that can be controlled by any one of three switches. One switch is the master on/off switch. If it is off, the lights are off. When the master switch is on, a change in the position of one of the other switches (from up to down or from down to up) will cause the light to change state. A system to do 1 bit of binary addition. It has three inputs (the 2 bits to be added plus the carry from the next lower order bit) and produces two outputs, a sum bit and a carry to the next higher order position.

Illustrations A system that has as its input the code for a decimal digit, and produces as its output the signals to drive a seven-segment display, such as those on most digital watches and numeric displays. A system with nine inputs, representing two 4-bit binary numbers and a carry input, and one 5-bit output, representing the sum. (Each input number can range from 0 to 15; the output can range from 0 to 31.)

Design Steps Represent each of the inputs and output in binary. This is sometimes taken care of in the problem statement (ex 1, 3, 5) Formalize the design specification either in the form of a truth table or of an algebraic expression. There are 2n input combinations for n inputs in a truth table. Truth tables are written in binary order to avoid omissions. If necessary, break the problem into smaller sub-problems before or after creating the truth tables.

Design Steps Simplify the description. Most times expressions have to be converted to algebraic forms Several techniques exist for reducing complexity of algebraic forms Implement the system with the available components, subject to the design objectives and constraints. Gates are the most common components A gate is a network with one output The less number of gates required, the more desirable the system is, since each signal passing through a gate introduces a delay in the system. More complex systems can be used in addition to gates (ex. Adders, decoders, e.t.c.).

Don’t Care Conditions Don’t cares occur when The output is not specified for all input combinations, so for the remaining input combinations, it doesn’t matter There are input combinations that don’t occur in the system Flip-flops – one systems drives another When we just don’t care Don’t cares are represented by X in a truth table. The output of the combination could either be a 1 or a 0.

Developing Truth Tables A system with four inputs, A, B, C, and D, and one output, Z, such that Z = 1 iff three of the inputs are 1.

A single light (that can be on or off) that can be controlled by any one of three switches. One switch is the master on/off switch. If it is off, the lights are off. When the master switch is on, a change in the position of one of the other switches (from up to down or from down to up) will cause the light to change state.

4. A system that has as its input the code for a decimal digit, and produces as its output the signals to drive a seven-segment display

Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, bin, and inputs x, y, that produces an a difference output, d, and a borrow output, bout. bin x y bout d 1 ? 0 0 0 1 1 0 1 1

Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, bin, and inputs x, y, that produces an a difference output, d, and a borrow output, bout. bin x y bout d 1 ? 0 0 0 1 1 0 1 1

Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, bin, and inputs x, y, that produces an a difference output, d, and a borrow output, bout. bin x y bout d 1 ? 0 0 0 1 1 0 1 1

Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, bin, and inputs x, y, that produces an a difference output, d, and a borrow output, bout. bin x y bout d 1 ? 0 0 0 1 1 0 1 1

Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, bin, and inputs x, y, that produces an a difference output, d, and a borrow output, bout. bin x y bout d 1 ? 0 0 0 1 1 0 1 1

Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, bin, and inputs x, y, that produces an a difference output, d, and a borrow output, bout. bin x y bout d 1 ? 0 0 0 1 1 0 1 1

Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, bin, and inputs x, y, that produces an a difference output, d, and a borrow output, bout. bin x y bout d 1 ? 0 0 0 1 1 0 1 1

Developing Truth Tables Example Truth table for a 1-bit full subtractor with a borrow input, bin, and inputs x, y, that produces an a difference output, d, and a borrow output, bout. bin x y bout d 1

Switching Algebra Simplify the description. Most times expressions have to be converted to algebraic forms Several techniques exist for reducing complexity of algebraic forms Implement the system with the available components, subject to the design objectives and constraints. Gates are the most common components A gate is a network with one output The less number of gates required, the more desirable the system is, since each signal passing through a gate introduces a delay in the system. More complex systems can be used in addition to gates (ex. Adders, decoders, e.t.c.).

Definitions Literal: The appearance of a variable or its complement. Product Term: one or more literals connected by AND operators. Standard product term: Also called minterm product term that includes each variable of the problem, either uncomplemented or complemented. Sum of products expression (often abbreviated SOP) one or more product terms connected by OR operators. A canonical sum or sum of standard product terms: a sum of products expression where all of the terms are standard product terms.

Definitions A Minimum Sum of Products expression: one of those SOP expressions for a function that has the fewest number of product terms. If there is more than one expression with the fewest number of terms, then minimum is defined as one or more of those expressions with the fewest number of literals. (1) xyz + xyz + xyz + xyz + xyz 5 terms, 15 literals (2) xy + xy + xyz 3 terms, 7 literals (3) xy + xy + xz 3 terms, 6 literals (4) xy + xy + yz 3 terms, 6 literals

Simplification xyz + xyz + xyz + xyz + xyz 5 terms, 15 literals = (x’yz’+x’yz)+(xyz + xyz) + xyz associative p2 = x’y(z+z’) + xy’(z+z’) + xyz distributive p8 = x’y.1 +xy’.1 +xyz complement p5 = x’y + xy’ + xyz identity p3 Down to three terms and seven literals

Simplification Reduce the number of literals by adding a second copy of xy’z (or x’yz), based on P6a – indempotency. xyz + xyz + xyz + xyz + xyz + xy’z 5 terms, 15 literals = (x’yz’+x’yz)+(xyz + xyz) + (xyz + xy’z) associative p2 = x’y + xy + xz adjacency p9 Down to three terms and six literals

Simplification

Simplification

Definitions Sum Term: one or more literals connected by OR operators. Standard sum term: also called a maxterm a sum term that includes each variable of the problem, either uncomplemented or complemented. Product of sums expression (POS): one or more sum terms connected by AND operators. Canonical product or product of standard sum terms: a product of sums expression where all of the terms are standard sum terms. SOP: xy + xy + xyz POS: (x + y)(x + y)(x + z) both: x + y + z or xyz neither: x(w + yz) or z + wxy + v(xz + w)

Simplification of Functions in Maxterm Form g = (w’ + x’ + y) (w + x’+ y + z’) = x’ + y + w’(w + z’) distributive (P8b) = x’ + y + w’z’ simplification (p10b) = (x’ + y + w’) (x’ + y + z’) distributive (P8b)

Implementation of Logic Gates f = x’y + xy’ + xz Minimum sum of product implementation of f. Circuit with only uncomplemented inputs.

Implementation of Logic Gates

Implementation of Logic Gates d = n’+c(h+s) (n+c’(h+s)) d = (n’c) + (hs) + n(hs) + c d = n’c(h+s) + n(c’+(hs)) D = n’c(ns) + n(hs)c =

De Morgan’s Theorem P11a. (a+b)’ = a’b’ P11b. (ab)’ = a’+b’ Please note: (a’+b’) != a’+b’ (ab)’ != a’b’ Proof of DeMorgan’s theorem. De Morgan’s Theorem is generally used to find the complement of an expression

De Morgan’s Theorem - Example Find the complement of f = wx’y +xy’ +wxz Note that f is in SOP so f’ will be in POS We could apply DeMorgan’s Theorem repeatdely f’ = (wx’y +xy’ +wxz)’ f’ = (wx’y)’(xy’)’(wxz)’ f’ = (w’x+y’)(x’+y)(w’+x’+z’) Or we could follow these set of rules Complement each variable Replace every AND by Or and every OR by AND – but make sure you keep the order of operation

De Morgan’s Theorem - Example Find the complement of f = ab +b’c + c’d f’ = (a’ + b’+ b + c’ + c + d’) f’ = (a’ + b’+ b + c’ + c + d’)’ f’ = a’b’+bc’+cd’ f’ = (a’ + b’)( b + c’) (c + d’) f’ = (a’ + b’)’( b + c’)’(c + d’)’

In groups 1 2e,f 3f 5 8 12a 13c 14 18

From the truth table to Algebraic Expressions f = ab + ab + ab

From the truth table to Algebraic Expressions

Example f(A,B,C) = Σm(1,2,3,6,7) = ? ABC f f’ 000 1 001 010 011 100 101 110 111 A’B’C’ + AB’C’ + AB’C B + C + D + G + H A’B’C + A’BC’ + A’BC + ABC’+ABC ABC’ + AB’C + AB’C’+ A’B’C + A’b ABC + A’BC+A’BC’ f’(A,B,C) = ? Σm(1,2,3,6,7)’ Σm(0,4,5) Σm(A’B’C’ + AB’C’ + AB’C)

Don’t Cares Input f 000 001 X 010 1 011 100 101 110 111 f(A,B,C) = Σm(2,3,6,7)+ Σd(1,5)

Chapter 3: Karnaugh Maps

Riddle Three people check into a hotel. They pay $30 to the manager and go to their room. The manager suddenly remembers that the room rate is $25 and gives $5 to the bellboy to return to the people. On the way to the room the bellboy reasons that $5 would be difficult to share among three people so he pockets $2 and gives $1 to each person. Now each person paid $10 and got back $1. So they paid $9 each, totalling $27. The bellboy has $2, totalling $29. Where is the missing $1?

Introduction to Karnaugh Maps If implemented correctly, they almost always produce a minimum solution. They are more straightforward that algebraic manipulations They generally produce SOPs, but POS can be generated from their complements if required.

Two-variable Karnaugh maps 1 B B’ A’ A A’B’ AB’ B 1 A’B AB A 1 B m0 m2 1 m1 m3

Three-variable Karnaugh maps Product terms corresponding to groups of two.

Four-variable Karnaugh maps

Implicants An implicant of a function is a product term. From the point of view of the map, an implicant is a rectangle of 1, 2, 4, 8, . . . (any power of 2) 1’s. That rectangle may not include any 0’s. Example: f = A’B’C’D’+A’B’CD+A’BCD+AB’CD+ABC’D’+ABC’D+ABCD AB 00 01 11 10 CD 00 1 1 01 1 11 1 1 1 1 10

Implicants The implicants of f are: Minterms (1 implicant) ABCD Groups of 2 ACD BCD ACD BCD ABC’ ABD Groups of 4 CD

Prime and Essential Prime Implicants an implicant that (from the point of view of the map) is not fully contained in any one other implicant. Essential Prime Implicant: a prime implicant that includes at least one 1 that is not included in any other prime implicant. AB 00 01 11 10 CD 00 1 1 01 1 11 1 1 1 1 10

Minimum SOP Expressions From Karnaugh Maps

Minimum SOP Expressions From Karnaugh Maps Find all essential prime implicants. Circle them on the map and mark the minterm(s) that make them essential with an asterisk (*). 2. Find enough other prime implicants to cover the function. Do this using two criteria: a. Choose a prime implicant that covers as many new 1’s (that is, those not already covered by a chosen prime implicant). b. Avoid leaving isolated uncovered 1’s. The main idea is To Have all ones covered To Have as few terms as possible To have several rectangles with more 1’s and few rectangles with less 1’s

Example f = w’x’y’z’+w’xy’z’+ w’xy’z+ w’xyz+ wx’y’z’+ w’xyz+ wxy’z’+ wxyz AB 00 01 11 10 CD * * * 00 1 1 1 1 unnecessary 01 1 11 1 * 1 1 10 f = y’z’+wyz+w’xz

In Groups Try problem 2a f = b + a' c

In Groups f = b + a' c

Don’t Cares Prime implicant A rectangle of 1, 2, 4, 8, . . . 1’s or X’s not included in any one larger rectangle. From the point of view of finding prime implicants, X’s (don’t cares) are treated as 1’s. Essential prime implicant A prime implicant that covers at least one 1 not covered by any other prime implicant (as always). Don’t cares (X’s) do not make a prime implicant essential.

Example f = Σm(1,7,10,11,13) + Σd(5,8,15) AB 00 01 11 10 CD 00 x Use don’t cares to get as many minterms in each tem as possible 1 01 1 x 11 1 x 1 10 1 F = BD + ACD + ABC

In groups Try Problem 4c f1 = x' z' + w' x y' + w x y + y' z’ f2 = x' z' + w' x y' + w x y + w z'

In groups For the following problem, find the minimum SOP expression within the options given h(a,b,c) = Σm(0,1,5) + d(3,4,6,7) h = a'b' + c + a h = a + c + b’ h = c + b’ h = b’ h = c

Homework Problems 1-4 f1 = x' z' + w' x y' + w x y + y' z’ f2 = x' z' + w' x y' + w x y + w z'

Group Exercises 2b,f 3b 4a 5e

Implementation of Two Functions

Example F = A’B’C’+A’BC’+ABC’+ABC; G = A’B’C+A’BC+ABC’+ABC 1 1 1 1 1 1 00 01 11 10 00 01 11 10 C C 1 1 1 1 1 1 1 1 1 1 F = A’C’+AB G = A’C+AB

Example F = AB + ABC G = AB + BC F = AB + ABC G = AB + ABC

Example f = ab + bc g = ab + ac f = ab + abc g = ab + abc

Example F = AC + ACD + ABC G = AC + ACD + ABC

Try

NAND, NOR Many electronic systems automatically invert gates Easier to fabricate with electronic components Basic gates used in integrated circuits (IC) digital logic families. NAND gate universal gate Could be used to construct any logic gate

NAND gates. Alternate symbol for NAND. Symbols for NOR gate.

NAND Gate Implementation When we have a circuit consisting of AND and OR gates such that the output of the circuit comes from an OR, the inputs to all OR gates come either from a system input or from the output of an AND, and the inputs to all AND gates come either from a system input or from the output of an OR. All gates are replaced by NAND gates, and any input coming directly into an OR is complemented.

Example Try: g = wx(y+z)+x’y

NOR Gate Implementation When we have a circuit consisting of AND and OR gates such that the output of the circuit comes from an AND, the inputs to all OR gates come either from a system input or from the output of an AND, and the inputs to all AND gates come either from a system input or from the output of an OR. All gates are replaced by NOR gates, and any input coming directly into an AND is complemented.

Example Try: g = (x+y’)(x’+y)(x’+z)

XOR and XNOR A xor B is 1 if a = 1 or b is 1 and 0 if both are 1 or 0; Develop a truth table for XOR

Chapter 4: Designing Combinational Systems Uchechukwu Ofoegbu Temple University Chapter 4: Designing Combinational Systems

Gate Delay ((1.1)’.1)’ = 1 ((1.0)’.0)’ = 1 ((0.1)’.1)’ = 0 ((0.1)’.0)’ = 1 ((1.1)’.1)’ = 1

One-bit Carry Ripple Adder s = sum cout – carry-out a, b = added bits C = carry in S = a’b’c+a’bc’+ab’c’+abc cout = a’bc+ab’c+abc’+abc = bc+ac+ab S = c(a’b’+ab)+c’(ab’+a’b) cout = c’(a+b)+ab S = c(aΦb)’+c’(aΦb) = c Φ(aΦb) Xor can be replaced with 4 two input NAND gates cout = c(aΦb)+ab a b c cout s 1 11 two-input NAND, three not gates 2 two-input XOR, 3 two-input NANDs, 1 three-input OR 5 three-input NAND, 3 two-input NAND, 1 four-input NAND, and three not gates if complemented inputs are not available

One-bit Full Binary Adder Gate implementation for the One-bit Full Adder n-bit “ripple-carry” binary adder Worst case propagation delay – 2n time units; Gate delay=1

Gate Delay through a 1-bit Adder Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

Gate Delay through an n-bit Adder Delay from inputs to cout + (n-2)*delay from cin to cout + Max(delay from cin to cout or cin to s) Total delay does not have to be so long!! For the multilevel adder: 5∆ + 2(n-2) ∆ + 3 ∆ = (2n+4) ∆ What is the delay for a 64 bit adder?

Gate Delay Improvements SOP minimization for two-bit adders Complex equations Fan-in limitations With a maximum fan-in of 7, adding n-bit would have a total delay of (n+1)∆ Four-bit adders 7483, 7483A, 74283 – differ only in pin connections Produces the sum with four-level inputs Uses combination of NAND, NOR, AND, NOT and XOR gates Delay from cin to cout = 3∆ Total delay = of (3/4 n+1)∆ 4-bit adders are cascaded for larger adders

One-bit Full Binary Adder c s Gate implementation for the One-bit Full Adder Cout n-bit “ripple-carry” binary adder Worst case propagation delay – 2n time units; Gate delay=1

Gate Delay Improvements Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

Gate Delay Improvements Carry-Look-Ahead Adder Carry generate signal (g) is 1 if that stage of the adder has a carryout of 1 whether or not there was a carry-in Carry propagate signal (p) is 1 if that stage of the adder has a carryout of 1 if he carry-in is 1 Both g and p can be generated for all n bits in 1 gate delay. The carry out is 1 if the last bit generated a carry, or if it propagated a carry and the stage below it generated one. All the carries can be generated in 2 additional delays after g and p are available, independent of n. All sums can be generated in 4∆, independent of n.

One-bit Full Binary Subtractor/Adder Subtract y from x , with a borrow-in from the previous bit position, bin d: difference bout: borrow-out x y bin bout d 1

Organization of a 1-bit comparator Compares two numbers to determine if A is less than B A is equal to B A if greater than B Can be extended to any bit size

Truth Table for Simple 1-bit Comparator Y: A=B 1 In groups, come up with a minimum SOP expression for this simple comparator. Assume all inputs are available in both complimented and uncomplemented versions, design a logic circuit for your algebraic expression What is the minimum delay for your design

Group Work 1 3 5 Homework: 2, 4, 7,

Binary Decoders Selects one of several outputs when activated n-bit binary number results in 2n output lines

Binary Decoders Selected output is high

Binary Decoders Selected output is low

Binary Decoders Selected output is high only when Enable bit is high or Enable Prime is low

Binary Decoders Active Low and three enable bits Active when ALL THREE enable bits are active

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Binary Encoders A0 A1 A2 A3 z0 z1 Exact Opposite of a binary decoder What is the difference between Device A0 and when there is no device signaling? Exact Opposite of a binary decoder Used to select a device from several possible devices If only one of the inputs can be 1, then the truth table for a 4-2 encoder is: A0 A1 A2 A3 z0 z1 1 Z0 =A2+A3 Z1 =A1+A3

Priority Encoders

Multiplexers A switch that is used to pass one input as a function of select inputs

Multiplexers

Group Work 10 – assume you have 4-input NAND also available 13*

Programmable Logic Devices Also known as gate arrays Involves gate diagrams combinational circuits with lines for all possible connection

Programmable Logic Devices - Illustration Base array is manufactured first Each connection is added when needed based on user specifications

Programmable Logic Devices - Illustration Field Programmable Gate Arrays (FPGAs) A fuse in connected in the midst of each connection line If the connection is not wanted, the fuse is blown

Programmable Logic Devices - Illustration Field Programmable Gate Arrays (FPGAs) Unprogrammed and-gate. Unprogrammed or-gate. Programmed and-gate realizing the term ac. Programmed or-gate realizing the term a + b. Special notation for an and-gate having all its input fuses intact. Special notation for an or-gate having all its input fuses intact. And-gate with nonfusible inputs. Or-gate with nonfusible inputs.

Programmable ROMs W(A, B, C, D) = m(3, 7, 8, 9, 11, 15) X(A, B, C, D) = m(3, 4, 5, 7, 10, 14, 15) Y(A, B, C, D) = m(1, 5, 7, 11, 15) You only need a list of minterms One AND gate for each minterm Appropriate minterm gates are connected to each output

Programmable Logic Arrays - PLAs You only need SOP expressions Main concern is the number of AND gates available You may use just a sum of minterms, or minimize each function or maximize charing W = ABC + ACD + ACD X = ABC + ACD + ACD + BCD Y = ACD + ACD + BCD 7 terms W = ABC + CD X = ABC + ACD + ACD + (BCD or ABC) Y = ACD + ACD + (BCD or A’BD) 8 or 9 terms depending on if we choose BCD

Programmable Array Logic - PAL Each output comes from an OR gate that has its own group of AND gates W = ABC + CD Y = ABC + ACD + ACD + {BCD or ABC} Z = ACD + ACD + {ABD or BCD}

Chapter 5: Analysis of Sequential Systems Uchechukwu Ofoegbu Temple University Chapter 5: Analysis of Sequential Systems

Sequential Logic Networks Combinational logic networks Outputs at any given time depends only on the input at that time Each output is represented by an algebraic function of the inputs Sequential logic networks Outputs depend on past and present inputs Past inputs must be stored – memory! Synchronous sequential network behavior determined by values of the signal at discrete instants of time (clock) Asynchronous sequential networks behavior immediately affected by the inputs changes

Clocks Frequency = ? Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

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Definitions State: Timing trace: State table: State diagram what is stored in memory stored in binary devices Timing trace: a set of values for the input and output at consecutive clock times and sometimes the state or other variables of the system, as well. State table: shows for each input combination and each state, what the output is and what the next state is, that is, what is to be stored in memory after the next clock. State diagram a graphical representation of the state table.

Example A system with one input x and one output z such that z = 1 if x has been 1 at least three consecutive clock times. Moore Model Output: depends only on the state of the system does not depend on the present input occurs after desired pattern

Mealy Model Output depends on present state as well as present input 1

Latches Simple binary storage device Consist of two or more gates Involves feedback Output of one gate is connected to input of another Inputs respond to outputs immediately Example: S-R Latch – Q holds the latch value 1 1 Q’ 1 P = (S + Q) Q = (R + P) P’ 1 1 1 inactive

Flip Flops Clocked binary storage device Value normally changes on appropriate clock transitions (except for special circumstances) Could have one or two outputs State of the flip flop Complement of the state Output can be described as function of input and present state

D – Flip Flops Simplest Flip Flop Stands for Delay Output = input delayed until next clock transition

Timing Diagram for D – Flip Flops Is this leading or trailing edge?

Two D – Flip Flops Output of 1 is input of 2 Output of 2 is output of 1 delayed

Clear and Preset Inputs Clear forces the output to 1 immediately Preset forces the output to 0 immediately Both can’t be 0 Flip flop is normal when both are 1

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S-R – Flip Flops Sets or Resets the data If both S and R are low, output remains unchanged Both can’t be high q* = S + Rq

S-R – Flip Flops

T – Flip Flops Changes state if input is 1 q* = T  q

J-K – Flip Flops J Sets and K resets the data If both J and K are low, output remains unchanged If both J and K are high, state changes q* = Jq + Kq

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Group Work Pg 314 1a 1/1 0/1 1/0 x 1 0 1 1 0 0 0 1 q1 0 0 0 1 0 1 0 0 1 0 10 q2 0 0 1 1 1 0 0 1 1 1 z 1 0 0 0 0 1 0 0 ? 0 00 0/0 10 0/0 11 1/0 01 0/1 1/0 Mealy or More? x 1 0 1 1 0 0 0 1 q1 0 0 0 1 0 1 0 0 1 0 10 q2 0 0 1 1 1 0 0 1 1 1 z 1 0 0 0 0 1 0 0 ? 0

Group Work Pg 314 4a

Analysis of Sequential Circuits

Group Work Pg 314 6 Q* = A  B

Group Work Pg 314 8a, b, c, d

Chapter 6: The Design of Digital Systems Uchechukwu Ofoegbu Temple University Chapter 6: The Design of Digital Systems

Example A system with one input x and one output z such that z = 1 if x has been 1 at least three consecutive clock times.

Design steps Step 1: From a word description, determine what needs to be stored in memory, that is, what are the possible states. Step 2: If necessary, code the inputs and outputs in binary. Step 3: Derive a state table or state diagram to describe the behavior of the system. Step 4: Use state reduction techniques to find a state table that produces the same input/output behavior, but has fewer states. Step 5: Choose a state assignment, that is, code the states in binary. Step 6: Choose a flip flop type and derive the flip flop input maps or tables. Step 7: Produce the logic equation and draw a block diagram (as in the case of combinational systems).

General Design Derive the equations for the next state and the output

D Flip Flop Design

D Flip Flop Design

J-K Flip Flop Design

J-K Flip Flop Design

S-R Flip Flop Design Derive the equations for the next state and the output

T Flip Flop Design Derive the equations for the next state and the output

Group Problem 2a SR: A- 0 X B- 1 0 C- 0 1 D- X 0 JK: A- 0 X B- 1 X C- X 1 D- X 0 TA TB: A- 1 1 B- X X C- 0 0 D- 1 0 E- 0 1

Group Problem In groups, obtain the other equations! Which flip-flop has the least delay?

Design of Synchronous Counters Synchronous counters go through a fixed sequence of states on successive clocks Most counters usually have no data inputs, just clock inputs Counter outputs are usually the next-state (i.e. is the flip flop values Example: 4-bit binary counter (four flip flops with a 0-15 cycle)

Design of Synchronous Counters In groups of two, design the counter using: D flip flops JK flip flops JA = KA = 1 JB = KB = A JC = KC = BA JD = KD = CBA DA = A DB = B’A + BA’ DC = CB’+CA’+C’BA DD = DC’ + DB’ + DA’ + D’CBA

Group Problem 8 e JK: A- 0 X B- 1 X C- X 1 D- X 0 E- X X

Registers Collection of flip-flops, which function is to hold information within a system A finite number of flips-flops => finite number of values stored in a register – content of register Shift register: moves the data one place to the right on each clock input

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