80x86

80x86 80186 Intel 80186 is a microprocessor and microcontroller introduced in 1982. It was based on the Intel 8086, & like it, had a 16-bit external data bus multiplexed with a 20-bit address bus. 68 pins 29,000 transistors Added 7 new instructions: push all, pop all, etc. 1982 ~ Sept. 2007.

80286 / iAPX 286 February 1, 1982 Bus Width: 16 bits data, 24 bits address. Included memory protection hardware to support multitasking operating systems with per-process address space Number of Transistors 134,000 Addressable memory 16 MB 3~6X the performance of the 8086

4 independent units: address unit, bus unit, instruction unit and execution unit, which formed a pipeline significantly increasing the performance. In computing, a pipeline is a set of data processing elements connected in series, so that the output of one element is the input of the next one. The elements of a pipeline are often executed in parallel or in time-sliced fashion; in that case, some amount of buffer storage is often inserted between elements.

386DX Introduced October 17, 1985 Bus Width 32 bits data, 32 bits address Number of Transistors 275,000 Addressable memory 4 GB Virtual Memory – 64 TB First x86 chip to handle 32-bit data sets Used in desktop computing

…386SX June 16, 1988 a low cost version of the 80386 with a 16-bit data bus. The original 80386 was subsequently renamed i386DX to avoid confusion. However, Intel subsequently used the 'DX' suffix to refer to the floating-point capability of the i486DX.

…386EX Introduced August 1994 Variant of 80386SX intended for embedded systems Static core, i.e., may run as slowly (and thus, power efficiently) as desired, down to full halt Static core is a CPU chip that can be stopped simply by stopping the system clock oscillator that is driving it, and it will hold its state indefinitely and resume processing at the point it was stopped when the clock signal is restarted, as long as it is kept powered. It allows the use of less power, and is suitable for standby mode.

Used aboard several orbiting satellites and microsatellites On-chip peripherals: Clock and power management Timers/counters Watchdog timer Serial I/O units (sync and async) and parallel I/O DMA RAM refresh Used aboard several orbiting satellites and microsatellites Used in NASA's FlightLinux project

32-bit processors: the 80486 range ..486DX April ‘89 Bus width – 32 bits No. of transistors – 1.2 million Addressable memory 4 GB Virtual memory 1 TB Level 1 cache of 8 KB on chip Math coprocessor on chip 50X performance of the 8088 Used in Desktop computing and servers

32-bit processors: P5 micro-architecture -- Pentium Bus width 64 bits Address bus 32 bits Addressable Memory 4 GB Virtual Memory 64 TB Superscalar architecture Used in desktops 8 KB of instruction cache 8 KB of data cache P5 - Mar ’93 ~ 3.1 mil transistors P54 3.2 mil tran.

Pentium II May 7, 1997 Pentium Pro with MMX and improved 16-bit performance 242-pin processor package Number of transistors 7.5 million 32 KB L1 cache 512 KB ½ bandwidth external L2 cache The only Pentium II that did not have the L2 cache at ½ bandwidth of the core was the Pentium II 450 PE.

Celeron [Pentium II-based] Introduced April 15, 1998 242-pin SEPP (Single Edge Processor Package) Number of transistors 7.5 million 66 MHz system bus clock rate 32 KB L1 cache No L2 cache Variants 266 MHz Introduced April 15, 1998 300 MHz Introduced June 9, 1998

Pentium III Feb. ‘99 Improved PII, i.e., P6-based core, now including Streaming SIMD Extensions (SSE) Number of transistors 9.5 million 512 KB ½ bandwidth L2 External cache 242-pin SECC2 (Single Edge Contact cartridge 2) processor package System Bus clock rate 100 MHz, 133 MHz (B-models)

Celeron (Pentium III Coppermine-based) Mar. 2000 28.1 mil trans. 66 MHz system bus clock rate, 100 MHz system bus clock rate from January 3, 2001 32 kB L1 cache 128 kB Advanced Transfer L2 cache

Pentium 4 Introduced April 2000 – July 2002

Celeron M Mar. 2003 64 KB L1 cache 512 KB L2 cache (integrated) SSE2 SIMD instructions No SpeedStep technology, is not part of the 'Centrino’ package

Intel Core Intel Core Duo T2700 2.33 GHz Intel Core Duo T2600 2.16 GHz Jan. 2006 Intel Core Duo T2700 2.33 GHz Intel Core Duo T2600 2.16 GHz Intel Core Duo T2500 2 GHz Intel Core Duo T2450 2 GHz Intel Core Duo T2400 1.83 GHz Intel Core Duo T2300 1.66 GHz Intel Core Duo T2050 1.6 GHz Intel Core Duo T2300e 1.66 GHz Intel Core Duo T2080 1.73 GHz Intel Core Duo L2500 1.83 GHz (low voltage, 15W TDP) Intel Core Duo L2400 1.66 GHz (low voltage, 15W TDP) Intel Core Duo L2300 1.5 GHz (low voltage, 15W TDP) Intel Core Duo U2500 1.2 GHz (ultra low voltage, 9W TDP) Intel Core Solo T1350 1.86 GHz (533 FSB) Intel Core Solo T1300 1.66 GHz Intel Core Solo T1200 1.5 GHz

8086 Interrupts Source: ‘Microprocessors and Interfacing’, by Douglas V Hall, Revised 2nd Edition Chapter 8

Interrupt Normal prog execution is interrupted by Some external signal, or A special instruction in the prog In response to an interrupt, the mp stops executing its normal prog & calls a procedure which ‘services’ the interrupt. An IRET instr at the end of the interrupt-service procedure returns execution to the interrupted prog.

8086 interrupt can come from 3 sources: Hardware interrupt: An external signal – applied To the nonmaskable interrupt (NMI) input pin, or To the interrupt (INTR) input pin Software interrupt: execution of the Interrupt instruction, INT Error condition: If some error condition occur by the execution of an instruction. E.g., divide-by-zero interrupt: If u attempt to divide an operand by zero, the 8086 will automatically interrupt the currently executing program

At the end of each instruction cycle, 8086 checks to see if any interrupts have been requested If an interrupt has been requested – the 8086 responds to the interrupt by stepping through the following series of major actions:

It decrements the stack pointer by 2 and pushes the flag register on the stack. It disables the INTR interrupt input – by clearing the interrupt flag (IF) in the flag register. It resets the trap flag (TF) in the flag register. It decrements the stack pointer by 2 and pushes the current code segment register contents on the stack. …

5. It decrements the stack pointer again by 2 and pushes the current instruction pointer contents on the stack. 6. It does an indirect fat jump to the start of the procedure you wrote to respond to the interrupt.

Divide-by-zero interrupt – Type 0 8086 will automatically do a type – 0 interrupt if The result of a DIV operation or An IDIV operation is too large to fit in the destination register  Too large!? Infinity!

So, write ur program so that u can manage – E.g., make sure that the divisor is not zero [to avoid infinity result]; and Do the division in several steps so that result of the division will never be too large. Another way: write an interrupt-service procedure which takes the desired action when an invalid division occurs.

Nonmaskable interrupt – type 2 8086 will automatically do a type 2 interrupt response when – it received a low-to-high [0 to 1] transition on its NMI input pin. Nonmaskable? – maskable = disable

This interrupt can not be disabled/masked – by any prog instructions. As this input cant be intentionally or accidentally disabled, external system must be taken care of.

e.g., We could have a pressure sensor on a large steam boiler – connected to the NMI input. If the pressure goes above a preset limit, the sensor will send an interrupt signal to the 8086. Type 2 interrupt-service procedure for this case might turn off the fuel to the boiler open a pressure-relief valve and sound an alarm!

Another exa. To save program data in case of a system power failure. When AC power fails – some external circuitry detects it. Sends an interrupt signal to the NMI input pin. Because of the large filter capacitors in most power supplied, the dc system power will remain for perhaps 50ms – after the AC power is gone.

This is enough time for a type 2 interrupt-service procedure to copy program data to some RAM, which has a battery backup power supply. When the AC power returns, program data can be restored from the battery-backed RAM, and the program can resume execution where it left off.