Pertemuan 19 External Memory: I Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1 Pertemuan 19 External Memory: I

Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Menghubungkan konsep eksternal memory dalam mendesain sistem komputer ( C4 ) ( No TIK : 9 )

Chapter 5. External Memory: I

SUM := for j:= to 9 do SUM := SUM + A(0,j) end A VE := SUM / 10 for i:= 9 do wn to do A(0,i) := A(0,i) / A VE end Figure 5.19. Task for example in Section 5.5.3.

Figure 5.20. Contents of a direct-mapped data cache in Example 5.1. Contents of data cache after pass: Block j = 1 j = 3 j = 5 j = 7 j = 9 i = 6 i = 4 i = 2 i = position A(0,0) A(0,2) A(0,4) A(0,6) A(0,8) A(0,6) A(0,4) A(0,2) A(0,0) 1 2 3 4 A(0,1) A(0,3) A(0,5) A(0,7) A(0,9) A(0,7) A(0,5) A(0,3) A(0,1) 5 6 7 Figure 5.20. Contents of a direct-mapped data cache in Example 5.1.

Contents of data cache after pass: Block j = 7 j = 8 j = 9 i = 1 i = position A(0,0) A(0,8) A(0,8) A(0,8) A(0,0) 1 A(0,1) A(0,1) A(0,9) A(0,1) A(0,1) 2 A(0,2) A(0,2) A(0,2) A(0,2) A(0,2) 3 A(0,3) A(0,3) A(0,3) A(0,3) A(0,3) 4 A(0,4) A(0,4) A(0,4) A(0,4) A(0,4) 5 A(0,5) A(0,5) A(0,5) A(0,5) A(0,5) 6 A(0,6) A(0,6) A(0,6) A(0,6) A(0,6) 7 A(0,7) A(0,7) A(0,7) A(0,7) A(0,7) Figure 5.21. Contents of an associative-mapped data cache in Example 5.1.

Contents of data cache after pass: j = 3 j = 7 j = 9 i = 4 i = 2 i = A(0,0) A(0,4) A(0,8) A(0,4) A(0,4) A(0,0) A(0,1) A(0,5) A(0,9) A(0,5) A(0,5) A(0,1) Set 0 A(0,2) A(0,6) A(0,6) A(0,6) A(0,2) A(0,2) A(0,3) A(0,7) A(0,7) A(0,7) A(0,3) A(0,3) Set 1 Figure 5.22. Contents of a set-associative-mapped data cache in Example 5.1.

Processing units L1 instruction L1 data cache cache Bus interface unit System bus Cache bus Main L2 cache Input/Output memory Figure 5.24. Caches and external connections in Pentium III processor.

Figure 5.25. Addressing multiple-module memory systems. k bits m bits Module Address in module MM address ABR DBR ABR DBR ABR DBR Module Module Module i n - 1 (a) Consecutive words in a module m bits k bits Address in module Module MM address ABR DBR ABR DBR ABR DBR Module Module Module i 2 k - 1 (b) Consecutive words in consecutive modules Figure 5.25. Addressing multiple-module memory systems.

Pertemuan 20 External Memory: II Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1 Pertemuan 20 External Memory: II

Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Menghubungkan konsep eksternal memory dalam mendesain sistem komputer ( C4 ) ( No TIK : 9 )

Chapter 5. External Memory: II

+ Figure 5.27. Virtual-memory address translation. Virtual address from processor Page table base register Page table address Virtual page number Offset + PAGE TABLE Control Page frame bits in memory Page frame Offset Physical address in main memory Figure 5.27. Virtual-memory address translation.

Figure 5.28. Use of an associative-mapped TLB. Virtual address from processor Virtual page number Offset TLB Virtual page Control Page frame number bits in memory No =? Yes Miss Hit Page frame Offset Physical address in main memory Figure 5.28. Use of an associative-mapped TLB.

Figure 5.30. Organization of one surface of a disk. Sector 0, track 1 Sector 3, track n Sector 0, track 0 Figure 5.30. Organization of one surface of a disk.

Figure 5.31. Disks connected to the system bus. Processor Main memory System bus Disk controller Disk drive Disk drive Figure 5.31. Disks connected to the system bus.

1 1 1 1 1 1 Figure 5.32. Optical disk. Aluminum Acrylic Label Pit Land Polycarbonate plastic (a) Cross-section Pit Land Reflection Reflection No reflection Source Detector Source Detector Source Detector (b) Transition from pit to land 1 1 1 1 1 1 (c) Stored binary pattern Figure 5.32. Optical disk.

Figure 5.33. Organization of data on magnetic tape. File File mark File mark • • 7 or 9 bits File gap Record Record Record Record gap gap Figure 5.33. Organization of data on magnetic tape.