TERMINATIONS Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology.

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Presentation transcript:

Terminations

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_2 Course outline Contents Digital Signal Model Non Ideal Behavior of Components High Speed Properties of Digital Gate Ground Planes Crosstalk Power Distribution TerminationsTerminations Line terminators End terminators Rise time (end terminators) Split termination Other end terminations Daisy chain Star topology Source terminators Resistance value (source terminators) Rise time (source terminators) Speed limitation (source terminators) Flat step response (source terminators) Drive current requirement (source) Capacitive termination Crosstalk in terminations Adjacent axial resistors Staggered resistors Adjacent SM resistors

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_3 Line terminators When does a system require terminating resistors? –Long lines  reflections (T DELAY > T RISE /3) –Short lines driving a capacitive load  ringing (damped oscillations) Ringing phenomenon and reflections have the same practical effect Without terminators signals transmission is impossible for long lines

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_4 End terminators The terminator is located at the receiving end of the transmission line. Each driving gate connects directly to its transmission line Properties: –The driving waveform propagates at full intensity all the way down the line –All reflections are damped by the termination –Received voltage and transmitted voltage are equal –Large drive current required in the HI state

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_5 Rise time ( end terminators ) Driving part –Thevenin equivalent driving impedance: Z 0 ||Z 0 Receiving part –Receiving gate model (CMOS, TTL, ECL)  Capacitor (C) Transmission line Z0Z0 R1R1 C Driving part of circuit Receiving part of circuit End-terminating resistance of Z 0 ohms Parasitic capacitor (load at gate input)

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_6 Rise time ( end terminators ) Given an incoming signal with a rise time of t r, the resulting rise time is: RC filter time constant: Rise time:

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_7 Rise time ( end terminators ) When a line is long compared to a rising edge, the impedance of its output is effectively Z 0. If the line length becomes comparable to the length of its rising edges, the impedance of its output decreases Eventually, for very short lines, the driving impedance is equal to the output impedance of the driving gate. We get a faster final rise time

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_8 Split termination C R2R2 R1R1 The ratio R 1 /R 2 controls the relative proportions of HI and LO drive current R 1 and R 2 selection –The parallel combination of R 1 and R 2 must equal Z 0 –Do not exceed I OH,Max –Do not exceed I OL,Max Split termination avoid problems related to large drive current required in the HI state

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_9 Other end terminations No possibility of proper termination Regardless of where we place terminators, signal energy from the driver reflects off at the juncture Main path Z0Z0 Z0Z0 Z0Z0

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_10 Other end terminations Possibility of correct termination: R 1 = R 2 = 2Z 0 Difficulty of fabricating lines of widely varying impedance on the same board Main path Z0Z0 2Z 0 Gnd R2R2 R1R1

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_11 Daisy chain Along an end-terminated line, a delayed reproduction of the input signal appears at each point It is possible to attach receivers to the line at any point  daisy chain configuration Main path Capacitance of each short stub adds to capacitive load of receiver (short compared to the length of a rising edge)

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_12 Star topology Each line must be correctly terminated

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_13 Source terminators Each driving gate is connected to its transmission line through a series resistor The value of the series resistor plus the output impedance of the driving gate should equal the characteristic impedance of the transmission line   SOURCE = 0 R1R1 Z0Z0 Characteristic Impedance, Z 0 +5 V GND

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_14 Source terminators Properties –The driving waveform is cut in half by the series resistor before it begins propagating –At the far end (an open circuit) the signal reflection coefficient is +1. The reflected signal is half intensity. The reflected signal plus the original incoming signal together bring the signal at the receiving end to a full level. –The reflected signal (half-size) propagates back along the line toward the source, where it damps out at the source termination.

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_15 Resistance value ( source terminations ) Practical drivers have small resistive output impedance (about 10  for an ECL). Source-terminating resistors values must therefore keep in account for this output impedance

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_16 Rise time ( source terminations ) When driving a capacitive load we get a respone which looks like a simple RC low-pass filter: The rise time is twice as long as the rise time of an end terminated circuit R 1 =Z 0 Z0Z0 +5 V GND Impedance we see at any point along the line, looking back toward the source The source termination should be as close as possible to driver gate

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_17 Speed limitation ( source terminations ) R1R1 +5 V GND Daisy chain topology –It’s necessary to wait for signal returning from the most far receiver –Limited transmission speed

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_18 Flat step response ( source terminations ) Source  resistive output impedance plus a little inductance Receiver  parasitic capacitive load It’s easier to eliminate reflections at the source than at the end of a transmission line Source terminations often yield a more nearly zero reflection coefficient than end terminators Flatter overall frequency response

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_19 Drive current requirement ( source ) Worst-case drive current required when a gate switches:  V/2Z 0 This current falls to zero after a time equal to the round-trip propagation delay of the line If the signals are infrequently switched, the average drive current is then small (although the large peak drive current)

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_20 Capacitive termination To reduce the quiescent power dissipation, sometimes capacitors are incorporated in end- termination circuits Gnd C R = Z 0 Z0Z0 Gnd +5V R 2 = 2Z 0 R 1 = 2Z 0 Z0Z0 Split termination

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_21 Capacitive termination RC is chosen very large compared to the signal clock time The drive circuit spends half its time in each state (DC-balanced)  the average value accumulated on capacitor C will be halfway between the HI and LO voltages Resistor R will have a voltage magnitude of  V/2 continuously impressed upon it

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_22 Capacitive termination By contrast in the split termination circuit, one or the other resistor always has the full  V across it, but each resistor is twice as big as R and so the average power dissipation is The additional wasted power dissipation flows from V CC directly to ground through R 1 and R 2

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_23 Capacitive termination If the driving gate stays in the HI state for too long, then capacitor C will charge up to the full HI voltage When the gate switches LO, the full  V will appear across R  drive current twice larger than DC-balanced case Problems with gate capability of sourcing the full amount of current  V/R

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_24 Crosstalk in terminations Input signal Trace #2 Trace #1 Y W Gnd Crosstalk in terminations is due both to mutual inductive and mutual capacitive coupling The inductive coupling is usually larger

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_25 Crosstalk in terminations Both magnetic and electrostatic coupling proportionally depend on the derivative of the applied input signal  it is possible to work with one overall coupling coefficient –V N = noise voltage –K = cross-coupling coefficient [  s] –R = resistance –  V = driving signal step size –t r = driving signal rise time

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_26 Adjacent axial resistors It is possible to estimate the crosstalk coefficient as: –K = crosstalk coupling coefficient –Y = length of resistors –H = centerline height above ground plane –W = separation between resistor centerlines

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_27 Staggered resistors Substitute Y with their overlap length Y’ Input signal Trace #2 Trace #1 Y’ W Gnd

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_28 Adjacent SM resistors Surface-mounted resistors, being naturally closer to the circuit board, exhibit lower crosstalk coefficient than axial components  parameter H decreases

@ Copyright F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyT_29 Next topic END