A 45nm 37.3GOPS/W Heterogeneous Multi-Core SoC ● Renesas Technology, Kodaira, Japan ● Hitachi, Kodaira, Japan ● Waseda University, Shinjuku, Japan ● Tokyo Institute of Technology, Yokohama, Japan

Architecture General Purpose Module ● 4x (CPU+FPU) ● Video CODEC ● DDR RAM controller Media Acceleration Module ● 4x (CPU+FPU) (36GFLOPS) ● 4x FE (41GLOPS) ● 2x MX-2 (36GFLOPS) ● DDR RAM controller Peripheral Module ● PCIe ● SATA ● SPU2 ● LBSC Intelligent clock gating for power management 3 separate buses with full interconnect

FE: dynamically reconfigurable processor ● ALU cells for arithmetic ● Load/Store cells for memory operations ● Local memory for buffering ● Optimal for image processing like optical flow ● 4bit granularity

Architecture General Purpose Module Media Acceleration Module Peripheral Module

SPEED / POWER / AREA GFLOPS3W (simulated)154 mm^ GFLOPS / W ● > Cell BE on 45nm SOI ● > TILE64 mesh interconnect CPU ● Faster than comparable archs. ● Designed for real time low power multimedia image processing, like in IP-TV