1 ECE 734 Final Project Presentation Fall 2000 By Manoj Geo Varghese MMX Technology: An Optimization Outlook.

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Presentation transcript:

1 ECE 734 Final Project Presentation Fall 2000 By Manoj Geo Varghese MMX Technology: An Optimization Outlook

2 Issues Facing MMX Today Latency. Cache Limits and Structure./Pipelining Floating Point Operation. Instruction Pairing/Mixing MMX instructions. Speed of Execution. Where are we in store for??

3 Next Generation Technology Intel ® Pentium ® 4 is an example Net Burst TM Architecture 1.5 GHz Processor. 400 MHz System Bus. Advanced Floating Point Operations. Trace Caches-Advanced Branch Prediction Algorithm. L1 Execution Cache + Data Cache. 256KB L2 Advanced Trace Cache. Hyper Pipelined Technology. 20 Level Pipelining. Rapid Execution Engine. Speed of ALU = 2 * Core frequency YES !!! (Atleast for integer operations) Do we stop here? Of Course No!!!!

4 But what about MMX Capability SSE2-Streaming SIMD Extensions new Instructions for Double Precision FP. Cache and Memory Management. Enable 3-D Graphics. Video Decoding/Encoding/ Speech Recognition. 128 bit MMX Registers. Separate Register for Data Movement. Visual internet- Voice over IP.

5 Work and Present Status Mentor Graphics Pipelining –Single level Clock cycle time reduced from ns !!! Imagine 20 Level Pipelining in P4!!! Cache Consideration. MMX instruction latencies. Pair MMX instructions. Mix MMX & Integer instructions. Study of Processors.