Recent experience with PCI-X 2.0 and PCI-E network interfaces and emerging server systems Yang Xia Caltech US LHC Network Working Group October 23, 2006.

Slides:



Advertisements
Similar presentations
DataTAG CERN Oct 2002 R. Hughes-Jones Manchester Initial Performance Measurements With DataTAG PCs Gigabit Ethernet NICs (Work in progress Oct 02)
Advertisements

Premio Predator G2 Workstation Training
Servidor Rack 2583ECU - x3250_M4 Express x3250 M4, Xeon 4C E3-1220v2 69W 3.1GHz/1600MHz/8MB, 1x4GB, O/Bay SS 3.5in SATA, SR C100, Multi- Burner, 300W p/s,
CALICE, Mar 2007, R. Hughes-Jones Manchester 1 Protocols Working with 10 Gigabit Ethernet Richard Hughes-Jones The University of Manchester
LCG TCP performance optimization for 10 Gb/s LHCOPN connections 1 on behalf of M. Bencivenni, T.Ferrari, D. De Girolamo, Stefano.
CdL was here DataTAG/WP7 Amsterdam June 2002 R. Hughes-Jones Manchester 1 EU DataGrid - Network Monitoring Richard Hughes-Jones, University of Manchester.
DataGrid WP7 Meeting CERN April 2002 R. Hughes-Jones Manchester Some Measurements on the SuperJANET 4 Production Network (UK Work in progress)
CALICE UCL, 20 Feb 2006, R. Hughes-Jones Manchester 1 10 Gigabit Ethernet Test Lab PCI-X Motherboards Related work & Initial tests Richard Hughes-Jones.
PFLDNet Argonne Feb 2004 R. Hughes-Jones Manchester 1 UDP Performance and PCI-X Activity of the Intel 10 Gigabit Ethernet Adapter on: HP rx2600 Dual Itanium.
ESLEA Bedfont Lakes Dec 04 Richard Hughes-Jones Network Measurement & Characterisation and the Challenge of SuperComputing SC200x.
CdL was here DataTAG CERN Sep 2002 R. Hughes-Jones Manchester 1 European Topology: NRNs & Geant SuperJANET4 CERN UvA Manc SURFnet RAL.
Computer Organization and Operating Systems AMD Athlon SMP Presented By: - Vinay Hegde ( ) Aashish Gupta ( )
Sockets vs. RDMA Interface over 10-Gigabit Networks: An In-depth Analysis of the Memory Traffic Bottleneck Pavan Balaji  Hemal V. Shah ¥ D. K. Panda 
The Chip Set. At one time, most of the functions of the chipset were performed by multiple, smaller controller chips Integrated to form a single set of.
 Model: ASUS SABERTOOTH Z77 Intel Series 7 Motherboard – ATX, Socket H2 (LGA115), Intel Z77 Express, 1866MHz DDR3, SATA III (6Gb/s), RAID, 8-CH Audio,
Dezső Sima Fall 2007 (Ver. 1.0)  Sima Dezső, 2007 Multisocket system architectures.
5.3 HS23 Blade Server. The HS23 blade server is a dual CPU socket blade running Intel´s new Xeon® processor, the E5-2600, and is the first IBM BladeCenter.
PHY 201 (Blum) Buses Warning: some of the terminology is used inconsistently within the field.
Computer Design Corby Milliron. Mother Board specs Model: Processor Socket Intel Processor Interface LGA1150 Form Factor ATX Processors Supported 4th.
Sven Ubik, Petr Žejdl CESNET TNC2008, Brugges, 19 May 2008 Passive monitoring of 10 Gb/s lines with PC hardware.
1.  Team Members  Team Leader: Adam Jackson  Communication Coordinator: Nick Ryan  Bader Al-Sabah  David Feely  Richard Jones  Faculty Advisor.
CMS Data Transfer Challenges LHCOPN-LHCONE meeting Michigan, Sept 15/16th, 2014 Azher Mughal Caltech.
ADVANCE FORENSIC WORKSTATION. SPECIFICATION Mother board : Xeon 5000 Series Server Board support 667MHz, 1066MHz and 1333MHz1 Processor : Two Intel Quad.
© David Kirk/NVIDIA and Wen-mei W. Hwu, 2007 ECE 498AL, University of Illinois, Urbana-Champaign ECE 498AL Lecture 6: GPU as part of the PC Architecture.
© Copyright IBM Corporation 2006 Course materials may not be reproduced in whole or in part without the prior written permission of IBM IBM BladeCenter.
Figure 1-2 Inside the computer case
TNC 2007 Bandwidth-on-demand to reach the optimal throughput of media Brecht Vermeulen Stijn Eeckhaut, Stijn De Smet, Bruno Volckaert, Joachim Vermeir,
Chipset Introduction The chipset is commonly used to refer to a set of specialized chips on a computer's motherboard or.
Large File Transfer on 20,000 km - Between Korea and Switzerland Yusung Kim, Daewon Kim, Joonbok Lee, Kilnam Chon
J. Bunn, D. Nae, H. Newman, S. Ravot, X. Su, Y. Xia California Institute of Technology High speed WAN data transfers for science Session Recent Results.
J. Bunn, D. Nae, H. Newman, S. Ravot, X. Su, Y. Xia California Institute of Technology State of the art in the use of long distance network International.
PCI Team 3: Adam Meyer, Christopher Koch,
MY PERSONAL COMPUTER Monica Sheffo. MOTHERBOARD  Model: Intel BOXDZ77GA-70K Intel Extreme Motherboard  Supported Processors: 2 nd generation Intel Core.
Evaluation of the LDC Computing Platform for Point 2 SuperMicro X6DHE-XB, X7DB8+ Andrey Shevel CERN PH-AID ALICE DAQ CERN 10 October 2006.
RiceNIC: A Reconfigurable and Programmable Gigabit Network Interface Card Jeff Shafer, Dr. Scott Rixner Rice Computer Architecture:
High Performance Computing Processors Felix Noble Mirayma V. Rodriguez Agnes Velez Electric and Computer Engineer Department August 25, 2004.
Network Tests at CHEP K. Kwon, D. Han, K. Cho, J.S. Suh, D. Son Center for High Energy Physics, KNU, Korea H. Park Supercomputing Center, KISTI, Korea.
Essentials components in Mobo The more important part in a mobo is the chipset. It make the interconnexions between all the other parts on the mobo.
Data transfer over the wide area network with a large round trip time H. Matsunaga, T. Isobe, T. Mashimo, H. Sakamoto, I. Ueda International Center for.
APAN 10Gbps End-to-End Performance Measurement Masaki Hirabaru (NICT), Takatoshi Ikeda (KDDI/NICT), and Yasuichi Kitamura (NICT) July 19, 2006 Network.
Securing and Monitoring 10GbE WAN Links Steven Carter Center for Computational Sciences Oak Ridge National Laboratory.
4 Dec 2006 Testing the machine (X7DBE-X) with 6 D-RORCs 1 Evaluation of the LDC Computing Platform for Point 2 SuperMicro X7DBE-X Andrey Shevel CERN PH-AID.
High TCP performance over wide area networks Arlington, VA May 8, 2002 Sylvain Ravot CalTech HENP Working Group.
ENW-9800 Copyright © PLANET Technology Corporation. All rights reserved. Dual 10Gbps SFP+ PCI Express Server Adapter.
Computer Architecture Project
DYNES Storage Infrastructure Artur Barczyk California Institute of Technology LHCOPN Meeting Geneva, October 07, 2010.
Harnessing Multicore Processors for High Speed Secure Transfer Raj Kettimuthu Argonne National Laboratory.
Masaki Hirabaru NICT Koganei 3rd e-VLBI Workshop October 6, 2004 Makuhari, Japan Performance Measurement on Large Bandwidth-Delay Product.
Computer Hardware The Processing Unit.
First of ALL Big appologize for Kei’s absence Hero of this year’s LSR achievement Takeshi in his experiment.
Weekly Report By: Devin Trejo Week of June 21, 2015-> June 28, 2015.
Sep. 17, 2002BESIII Review Meeting BESIII DAQ System BESIII Review Meeting IHEP · Beijing · China Sep , 2002.
Motherboard A motherboard allows all the parts of your computer to receive power and communicate with one another.
GNEW2004 CERN March 2004 R. Hughes-Jones Manchester 1 Lessons Learned in Grid Networking or How do we get end-2-end performance to Real Users ? Richard.
$ 1000 COMPUTER. EVGA 132-CK-NF79-A1 NVIDIA nForce 790i Ultra SLI Socket 775 ATX MB w/RAID, 3-Way SLI, DDR3 & Core 2 Extreme Support Supports up to 8.
Final EU Review - 24/03/2004 DataTAG is a project funded by the European Commission under contract IST Richard Hughes-Jones The University of.
Exploiting Task-level Concurrency in a Programmable Network Interface June 11, 2003 Hyong-youb Kim, Vijay S. Pai, and Scott Rixner Rice Computer Architecture.
S. Ravot, J. Bunn, H. Newman, Y. Xia, D. Nae California Institute of Technology CHEP 2004 Network Session September 1, 2004 Breaking the 1 GByte/sec Barrier?
L1/HLT trigger farm Bologna setup 0 By Gianluca Peco INFN Bologna Genève,
Lecture 2. General-Purpose Computer Systems Prof. Taeweon Suh Computer Science Education Korea University ECM586 Special Topics in Embedded Systems.
The ALICE Data-Acquisition Read-out Receiver Card C. Soós et al. (for the ALICE collaboration) LECC September 2004, Boston.
Open-source routing at 10Gb/s Olof Hagsand (KTH) Robert Olsson (Uppsala U) Bengt Görden (KTH) SNCNW May 2009 Project grants: Internetstiftelsen (IIS) Equipment:
This document contains information on a pre-launch desktop that is under NDA and is not yet available. Expected launch is: January 20, 2017.
Joint Genome Institute
NaNet Problem: lower communication latency and its fluctuations. How?
CALICE TDAQ Application Network Protocols 10 Gigabit Lab
Computer Hardware.
R. Hughes-Jones Manchester
Intel Desktop Board D945GTP
MB-NG Review High Performance Network Demonstration 21 April 2004
Presentation transcript:

Recent experience with PCI-X 2.0 and PCI-E network interfaces and emerging server systems Yang Xia Caltech US LHC Network Working Group October 23, 2006

Wire speed 10GbE cards Neterion’s Xframe II 10 Gigabit Ethernet PCI-X 2.0 –PCI-X MHz/64bit. Compatible with PCI-X 1.0 bus. –32MB Rx Frame Buffer. –Offload engine: TCP/UDP Checksum, LSO, LRO. –Support of PCI Message Signaled Interrupt (MSI) and PCI Extended Message Interrupt (MSI-X) –Fixed Optics (LR or SR). –System support PCI-X 2.0 bus: IBM x366 series –Native PCIe interface card will be available in 2007 Myricom’s 10GbE PCIe –PCIe 1.1 and PCIe 1.0a x8 (8 lane) –Optical XFP transceiver (SR & LR) & CX4 –Standard and half-height PCI faceplate –2MB local memory for firmware execution and for buffering packet headers.

10GbE Capable System – AMD Opteron Processor Opteron motherboards with PCIe support: Tyan: S2891 (1U), S2892, S4881 –AMD-8131 chipset for PCI-X 1.0 slots –nVidia nForce Pro 2200 chipset to support PCI Express x4, x16 slots Supermicro: H8DAR-T, H8DCi –nVidia nForce Pro AMD 8132 to support PCI Express x4, x16 slots –ServerWorks HT HT1000 –AMD-8132 chipset for PCI-X 1.0 slots Integrated memory controller. NUMA support: allows CPU to access local RAM without using the HyperTransport bus.

10GbE Capable System – Intel Xeon Processor IBM x366 system: Xeon MP 3.6GHz, 667MHz system bus, X3 Architechture, 6 available PCI-X MHz slots. Intel woodcrest processor motherboards: –e.g. Supermicro X7DBR-E (1U) & X7DBE Dual Intel Xeon GHz woodcrest processor (4 cores/system) Much improved Northbridge speed: Front-side bus is 64-bit wide, 1333MHz data bus that transfers data at 10.7 GB/sec. Unlike AMD's Opteron processors, none of Intel's forthcoming chips comes with an integrated memory controller. In future chips, it may integrate memory controllers, which let the processor get data from memory. DDR2 1GB 667MHZ ECC Fully buffered memory. PCIe x8 and PCI-X interface slots. 4 SATA disks in 1U form factor: - read ~220MB/s – write ~150MB/s (from FDT) 24 SATA disks on 2 Areca 1230 PCIe controllers - read ~650MB/s - write ~450MB/s

10GbE Capable System – Intel Xeon Processor Woodcrest will consume a maximum of 80 watts, previous Xeon processor use110-watt. SPECint power rating for woodcrest processor is ~17% less than Opteron 285 processor: –SPECint: 281.1watts vs 327.7watts. –Actual measurement: 220watts vs 259watts (~18% power reduction). CMSSW overall factor of 2 compare to Xeon and 1.5 compare to Opteron 248.

Block Diagram of the Intel 5000P Chipset PCIe x8 FSB 1333MHz

Neterion Xframe II WAN performance on USN  Caltech-Starlight-Caltech 155ms RTT network  Small 64MB TCP window size  8 TCP streams from Iperf  1hr average 9.2 Gbits/s  9.9Gbits/s performance in LAN connection.

Myri-10GbE PCIe LAN performance  Intel woodcrest 5160 system  Cisco GbE port with flowcontrol on.  Single TCP stream from Iperf  1hr average 9.88 Gbits/s

Myri-10GbE PCIe WAN performance on USN Single TCP Stream Multiple TCP Streams RHEL AS4.4 x86_64, Kernel ELsmp

Caltech/CERN SC’06 Demos Plan to use new Intel woodcrest systems in the booth from HP. Storage systems: Bluearc (IP), Data Direct Network (4Gbits/s FC)and Nimbus (iSCSI). Support from Cisco: chassis, new GbE module. Greater use of storage-to-storage transfers with PCIe NICs to match 10 Gbps links Disk-to-disk transfers of REAL scientific data. FDT: –A scalable Streaming Data Transfer application: coupled to VINCI dynamic circuit provisioning services; Intend to be integrated with dcache/SRM and other production storage systems. bbcp. Gridftp. Fully utilizes 10 Gig paths from Tampa to Caltech, CERN, Starlight and International sites (Korea via Gloriad, Brazil via Ampath).

SC’06 Available Network Resources Note: NLR circuits and A-wave need to be scheduled. NLR circuits are guaranteed to have dedicated 10 GE access for 1 hour at a time for any application.