Ryo Ichimiya et Yasuo Arai KEK/IPNS / Workshop on advanced detector technology for nuclear RIKEN SOI Pixel Détecteur

OUTLINE 1.Introduction of SOIPIX technology 2.Test Results 3.Issues & Solutions 4.Summary 1.Introduction of SOIPIX technology 2.Test Results 3.Issues & Solutions 4.Summary

KEK : Y. Unno, S. Terada, Y. Ikegami, T. Tsuboyama, T. Kohriki, Y. Ikemoto, T. Miyoshi, K. Tauchi, R. Ichimiya, Y. Fujita, D. Nio, A. Takeda Tsukuba Univ. : K. Hara, K. Shinsho Osaka Univ.: K. Hanagaki, J. Uchida Tohoku Univ. : Y. Onuki, Y. Horii, H. Yamamoto, Y. Sato, H. Katsurayama, Y. Ono Kyoto Univ. : T. Tsuru, H. Matsumoto, S. G. Ryu, S. Nakashima Kyoto U. of Education : R. Takashima JAXA/ISAS : H. Ikeda, D. Kobayashi, T. Wada, H. Nagata RIKEN(+SPring-8) : T. Hatsui, T. Kudo, A. Taketani. T. Kameshima, Y. Kirihara, M. Omodani, K. Kobayashi, S. Ono, T. Tatsumi LBNL : M. Battaglia, P. Denes, C. Vu, D. Contarato, P. Giubilato, L. Glesener FNAL : G. Deptuch, R. Yarema, M. Trimpl, R. Lipton, U. of Hawaii : G. Varner, M. Cooney, H. Hoedlmoser, H. Sahoo INP, Krakow : P. Kapusta, H. Palka INFN Padova : D. Bisello, S. Mattiazzo, D. Pantano Louvain-la-Neuve University : E. Cortina, E. Martin, L. Soungyee OKI Semiconductor (Miyagi) Co. Ltd. : K. Fukuda, I. Kurachi, M. Okihara, N. Kuriyama, H. Kasai.... KEK : Y. Unno, S. Terada, Y. Ikegami, T. Tsuboyama, T. Kohriki, Y. Ikemoto, T. Miyoshi, K. Tauchi, R. Ichimiya, Y. Fujita, D. Nio, A. Takeda Tsukuba Univ. : K. Hara, K. Shinsho Osaka Univ.: K. Hanagaki, J. Uchida Tohoku Univ. : Y. Onuki, Y. Horii, H. Yamamoto, Y. Sato, H. Katsurayama, Y. Ono Kyoto Univ. : T. Tsuru, H. Matsumoto, S. G. Ryu, S. Nakashima Kyoto U. of Education : R. Takashima JAXA/ISAS : H. Ikeda, D. Kobayashi, T. Wada, H. Nagata RIKEN(+SPring-8) : T. Hatsui, T. Kudo, A. Taketani. T. Kameshima, Y. Kirihara, M. Omodani, K. Kobayashi, S. Ono, T. Tatsumi LBNL : M. Battaglia, P. Denes, C. Vu, D. Contarato, P. Giubilato, L. Glesener FNAL : G. Deptuch, R. Yarema, M. Trimpl, R. Lipton, U. of Hawaii : G. Varner, M. Cooney, H. Hoedlmoser, H. Sahoo INP, Krakow : P. Kapusta, H. Palka INFN Padova : D. Bisello, S. Mattiazzo, D. Pantano Louvain-la-Neuve University : E. Cortina, E. Martin, L. Soungyee OKI Semiconductor (Miyagi) Co. Ltd. : K. Fukuda, I. Kurachi, M. Okihara, N. Kuriyama, H. Kasai.... SOI Pixel Collaboration 3

No mechanical bump bondings -> High Density(pitch Low parasitic Capacitance, High Sensitivity Fast signal and High resolution (Full Depletion: >200  m Si) Standard CMOS circuits can be built. Thin active Si layer (~40 nm) -> No Latch Up, Small SEE Cross section, larger LET threthold. Based on Industrial standard technology -> Fabricate in a commercial fabrication plant No mechanical bump bondings -> High Density(pitch Low parasitic Capacitance, High Sensitivity Fast signal and High resolution (Full Depletion: >200  m Si) Standard CMOS circuits can be built. Thin active Si layer (~40 nm) -> No Latch Up, Small SEE Cross section, larger LET threthold. Based on Industrial standard technology -> Fabricate in a commercial fabrication plant Monolithic detector using Bonded wafer (SOI : Silicon-on-Insulator) of Hi-R and Low-R Si layers. SOI Pixel Detector 4

OKI 0.2  m FD-SOI Pixel Process Process 0.2  m Low-Leakage Fully-Depleted SOI CMOS (OKI) 1 Poly, 4 (5) Metal layers, MIM Capacitor, DMOS option Core (I/O) Voltage = 1.8 (3.3) V SOI wafer Diameter: 200 mm , Top Si : Cz, ~18  -cm, p-type, ~40 nm thick Buried Oxide: 200 nm thick Handle wafer: Cz ~700  -cm (n-type), FZ: ~10k  -cm (n-type, p-type) up to 725  m thick BacksideThinned to 260  m and sputtered with Al (200 nm). An example of a SOI Pixel cross section 5 Depletion layer

1st Al p+ implant to Handle wafer & Metal contacts Copyright 2007 Oki Electric Industry Co.,Ltd Handle Wafer 6

MPW (Multi Project Wafer) run ~Twice per Year 7

88  -ray Integration Type Pixel (INTPIX) Size : 14  m x 14  m with CDS circuit Size : 14  m x 14  m with CDS circuit

9 Integration Type Pixel (INTPIX4) 10.2 mm 17x17  m, 512x832 (~430k ） pixels, 13 Analog Out, CDS circuit in each pixel. Largest Chip so far mm

10 X-ray imaging test for Integration Type Pixel (INTPIX4) A small dried sardine (“Niboshi” in Japanese) is used. Bias Voltage: 200V(Vback)Bias Voltage: 200V(Vback) 500 frame average500 frame average Integrating time: 250  sIntegrating time: 250  s X-ray tube(Mo): 20kV, 5mAX-ray tube(Mo): 20kV, 5mA INTPIX4 & NIBOSHI X- ray

115mm X-ray imaging test for Integration Type Pixel (INTPIX4) A small dried sardine (“Niboshi” in Japanese) is used. Bias Voltage: 200V(Vback)Bias Voltage: 200V(Vback) 500 frame avarage500 frame avarage Integrating time: 250  sIntegrating time: 250  s X-ray tube(Mo): 20kV, 5mAX-ray tube(Mo): 20kV, 5mA INTPIX4 & NIBOSHI

12 X-ray imaging test for Integration Type Pixel (INTPIX4) A small dried sardine (“Niboshi” in Japanese) is used. Bias Voltage: 200V(Vback)Bias Voltage: 200V(Vback) 500 frame avarage500 frame avarage Integrating time: 250  sIntegrating time: 250  s X-ray tube(Mo): 20kV, 5mAX-ray tube(Mo): 20kV, 5mA5mm5mm

X-ray imaging test for Integration Type Pixel (INTPIX4) A small dried sardine (“Niboshi” in Japanese) is used. Bias Voltage: 200V(Vback)Bias Voltage: 200V(Vback) 500 frame avarage500 frame avarage Integrating time: 250  sIntegrating time: 250  s X-ray tube(Mo): 20kV, 5mAX-ray tube(Mo): 20kV, 5mA5mm

X-ray Measurement with other SOI pixel 14 High Resolution Good Energy Measurement 20 lp/mm

Counting Type Pixel (CNTPIX5) 5 x15.4 mm 2 72 x 212 pixels 64um x 64 um pixel 5 x15.4 mm 2 72 x 212 pixels 64um x 64 um pixel Energy selection and Counting in each pixel Time Resolved Imaging 9bit x 8 15 Same architecture with HEP/NP pixels -> We are developing a prototype for next Belle II detector (SBPIX1). Same architecture with HEP/NP pixels -> We are developing a prototype for next Belle II detector (SBPIX1).

CNTPIX5 Pixel Layout 64x64 um 2 ~600 Tr/pix x 72 x 212 = 10,000,000 Trs 16

17 SOI Pixel Issues & Solutions a.Back Gate Effect : Sensor voltage affect Tr. characteristics  Buried P-Well (BPW) layer b.Wafer Thinning : Thin Sensor  TAIKO process c.Cross Talk & Radiation Hardness : Additional Shield layer  Double SOI Wafer d.Higher Circuit Density : Vertical (3D) Integration e.Thicker depletion layer : FZ wafer and back-side process f.Radiation tolerance: SEE immunity structure, BOX for TID  Double SOI Wafer a.Back Gate Effect : Sensor voltage affect Tr. characteristics  Buried P-Well (BPW) layer b.Wafer Thinning : Thin Sensor  TAIKO process c.Cross Talk & Radiation Hardness : Additional Shield layer  Double SOI Wafer d.Higher Circuit Density : Vertical (3D) Integration e.Thicker depletion layer : FZ wafer and back-side process f.Radiation tolerance: SEE immunity structure, BOX for TID  Double SOI Wafer

a. Back Gate Effect Front Gate and Back Gate are coupled. (Back Gate Effect) Front Gate and Back Gate are coupled. (Back Gate Effect) 18 Vg_back

BPW Implantation Suppress the back gate effect. Shrink pixel size without loosing sensitive area. Increase break down voltage with low dose region. Less electric field in the BOX which may improve radiation hardness. Suppress the back gate effect. Shrink pixel size without loosing sensitive area. Increase break down voltage with low dose region. Less electric field in the BOX which may improve radiation hardness. BPW P+ SOI Si Buried Oxide (BOX) Cut Top Si and BOX High Dose Cut Top Si and BOX High Dose Keep Top Si not affected Low Dose Keep Top Si not affected Low Dose Substrate Implantation PixelPeripheral Buried p-Well (BPW) 19

I d -V g and BPW w/o BPW with BPW=0V NMOS Back gate effect is suppressed by the BPW. shift back channel open 20

21 b. Wafer Thinning :TAIKO process Thinned to ~30um. Back side process still can be done after thinning. Thinned to ~30um. Back side process still can be done after thinning.

22 I-V Characteristic Before & After Thinning No difference seen after thinning. Normal operation confirmed. No difference seen after thinning. Normal operation confirmed. Thinned to 110 um and diced

23 additional conduction layer sensor circuit Increase radiation hardness by compensating Oxide/Interface Trap charge with middle layer bias. This also reduce cross talk between circuit and sensor Increase radiation hardness by compensating Oxide/Interface Trap charge with middle layer bias. This also reduce cross talk between circuit and sensor c. Double SOI Layer wafer under preparation

24 T-micro + OKI Semi + KEK/LBNL/Fermilab d. Vertical (3D) Integration Two chips are bonded with  -bump technology (~5 um pitch) of T-micro Co.

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27 FZ wafer of 260um is fully e. Wafer Resistivity : FZ SOI Wafer CZ wafer: 700 Ω cm FZ wafer: 10KΩ cm CZ wafer: 700 Ω cm FZ wafer: 10KΩ cm

28 SOI is Immune to Single Event Effect ＋－ ＋－ ＋－ ＋－ ＋－ ＋－ ＋－ ＋－ ＋－ ＋－ ＋－ Bulk Device Gate Gate Oxide Si ＋－ ＋－ ＋－ ＋－ SOI Device Gate ＋－ ＋－ ＋－ Si Buried Oxide Depletion Layer 28 But not necessary strong to Total Ionization Dose due to thick BOX layer Gate Si Buried Oxide ＋＋＋＋＋ Trapped Holes f. Radiation Tolerance

29 Leak Current and V Th resumes to nearly original value by biasing back side even after 100Mrad. before irradiation Vback= V p/cm 2 (~100 Mrad) p/cm 2 (~100 Mrad) Total Ionization Dose effect can be compensated by back bias f. Radiation Tolerance Double SOI may be a solution to compensate the TID effect.

30 Summary We could confirm basic performance of a new monolithic pixel detector technology, SOI Pixel. SOIPIX can be very thin detector with active circuit in each pixel. Main issue to realize the SOI pixel, back-gate effect, has been solved by Buried P-Well. Wafer was successfully thinned to 100 um with TAIKO process, and it is possible to thin down to ~30 um. SOIPIX is immune to the single event effect, and Total Ionization effect can be compensated by back side bias (Double SOI wafer). Vertical (3D) Integration R&D is on-going to increase integration level. With FZ wafer, thicker depletion layer achieved with lower bias voltage.

31 Supplement

KEK-OKI semi SOI Brief History '05. 7: Start Collaboration with OKI Semiconductor. '05.10: First Submission in VDEC 0.15 um MPW. '06.12: 1 st (and last) 0.15 um KEK MPW run. '07.3: 0.15 um lab. process line was closed. --> move to 0.2 um mass production line. '08.1: 1 st KEK SOI-MPW run. '09.2: 2 nd KEK SOI-MPW run. '09.8: 3 rd KEK SOI-MPW run. '10.1: 4 th KEK SOI-MPW run. '10.8: 5 th KEK SOI-MPW run. '11.1: 6 th KEK SOI-MPW run '05. 7: Start Collaboration with OKI Semiconductor. '05.10: First Submission in VDEC 0.15 um MPW. '06.12: 1 st (and last) 0.15 um KEK MPW run. '07.3: 0.15 um lab. process line was closed. --> move to 0.2 um mass production line. '08.1: 1 st KEK SOI-MPW run. '09.2: 2 nd KEK SOI-MPW run. '09.8: 3 rd KEK SOI-MPW run. '10.1: 4 th KEK SOI-MPW run. '10.8: 5 th KEK SOI-MPW run. '11.1: 6 th KEK SOI-MPW run 32

Readout system for SOIPIX We have developed a Ethernet-based (SiTCP) DAQ board for SOIPIX, named SEABAS (SOI EvAluation BoArd with Sitcp).We have developed a Ethernet-based (SiTCP) DAQ board for SOIPIX, named SEABAS (SOI EvAluation BoArd with Sitcp). Portable DAQ system; same software with Linux, Windows, Apple, etc.Portable DAQ system; same software with Linux, Windows, Apple, etc. 33 INTPIX4INTPIX4 Sub Board for INTPIX4 SEABASSEABAS DataTransfer Data Transfer by Ethernet ADC & DAC USERFPGAUSERFPGA 300mm300mm Bias Voltage inlet LV inlet

 -bumps fabrication 34 Copyright 2009 OKI semiconductor Co. Ltd. Minimum pitch: 5um T-Micro

LBNL 35

36 Energy Resolution 109Cd 22keV FWHM~7% Noise ~ 170e-

37 Infrared Laser (1064 nm) Response of Thinned Chip Full Depleted around 100V b. Wafer Thinning :TAIKO process

38 d. Nested BNW/BPW Structure Structure developed in cooperation between G. Deptuch (Fermilab) and I. Kurachi (OKI Semi) Signal is collected with the deep Buried P-well. Back gate and Cross Talk are shielded with the Buried N-well. Test chip is under process. Signal is collected with the deep Buried P-well. Back gate and Cross Talk are shielded with the Buried N-well. Test chip is under process. implant

39 Impurity Concentration

40 Before OxidationConventional SOI Process Improved SOI Process e. Wafer Resistivity : FZ SOI Wafer During the conventional SOI process, many slips were generated in the 8’’ FZ-SOI wafer. We optimized the process parameters, and succeeded to perform the process without creating many slips. Slips