Guided by - Prof. N A Gajjar Prepared by : Hemaxi Halpati : Priyank Hirani : Manish Jatiya : Rakesh Joshi : Piyush Kanani

Chart of preparation of presentation July August

Topic  OP-AMP feedback amplifier analysis.  Differential amplifier with one OP-AMP.  Differential amplifier with two OP-AMP.  Differential amplifier with three OP-AMP.  OP-AMP parameters.  Offset nulling methods.

Feedback in OP-AMP circuits  The structures of OP-AMP circuits using various types of negative feedback are shown in figure

Voltage – series feedback amplifier  The schematic diagram of non – inverting amplifier is as shown in figure.  From figure it is clear that voltage sampling is taking place on outside, because the feedback voltage is proportional to the output voltage.  And series mixing takes place at the input because the feedback voltage appears to be in series with input voltage.

Conti.  Type of negative feedback : voltage sampling + series mixing = voltage series feedback.  Closed loop gain : A VF = A V (R 1 + R F ) (Exact), A VF = 1 + R F (For ideal) R 1 + R F + A V R 1 R 1  Gain of feedback circuit B = V F = R 1 V O (R 1 + R F )  A VF = A V & R iF = R i 1 + A V B 1 + A V B  R oF = R o & f F = (1 + A V B) f o 1 + A V B

Voltage shunt feedback amplifier  The schematic diagram of an inverting amplifier is as shown in figure.  The feedback is proportional to the output voltage.  Hence it is voltage sampling and the feedback voltage appears in parallel (shunt) with the input voltage. Hence it is shunt mixing.

Conti.  Type of negative feedback : voltage sampling + shunt mixing = voltage shunt feedback.  Closed loop gain : A VF = - A V R 1 (Exact), A VF = - R F (For ideal) R 1 + R F + A V R 1 R 1  Gain of feedback circuit B = V F = R 1 & Attenuation factor K = R F V O (R 1 + R F ) (R 1 + R F )  A VF = - A V K & R iF = R i (Ideal) 1 + A V B  R OF = R o & f F = (1 + A V B) f o 1 + A V B A V

Differential amplifier  The differential amplifier is used to obtain the output proportional to the subtraction of two input voltages. The circuit diagram of the difference amplifier using OP- AMP is shown in figure.

Differential amplifier using one OP-AMP  The difference amplifier and subtractor circuit is used to obtain the subtraction of two input voltages.  The circuit diagram of the difference amplifier using OP-AMP is shown in figure.

Conti.  Output voltage, V O = R F (V 2 - V 1 ) R 1  Voltage gain, A D = - R F R 1  Input resistance, R iF1 = R 1 (If V 2 is grounded) R iF2 = (R 1 + R 2 )  For subtractor, R 1 = R F = R  Then output voltage, V O = ( R 2 – R 1 )

Differential amplifier with two OP-AMP  The gain and input resistance of the differential amplifier can be increased if we use two OP-AMPs.  The differential amplifier with two OP-AMPs is shown in figure.  The characteristics of this circuit are identical to those of non-inverting amplifier.  A 1 is the non-inverting amplifier whereas A 2 is difference amplifier.

Conti.  Output voltage of first stage, V 3 = 1 + R 1 V 2 R F  Voltage gain of first stage, A V1 = 1 + R F R 1  Total output voltage, V O = 1 + R F (V 1 - V 2 ) R 1  Total gain of the circuit, A D = 1 + R F R 1  Input resistance of first stage, R iF = R i (1 + Aβ) where, β = R 2 R 2 + R 3  Input resistance of second stage, R iF1 = R i (1 + Aβ) where, β = R R 1 + R F

Differential amplifier with three OP-AMPs  The difference amplifier discussed earlier has a low input impedence. Whereas the input impedence of a high quality instrumentation amplifier should be very high.  This problem of the difference amplifier can be overcome by using a buffer stage on the input side as shown in figure. Buffer is nothing but a unity gain voltage follower circuit.  The voltage gain of the buffer stage is 1. But it provides a very high input impedence. The gain of the circuit shown in figure is same as the gain of the difference amplifier discussed in the previous section.  The gain of difference amplifier can be varied by keeping the resistance R 2.

Conti.  Out put of difference amplifier, V O = R 2 (V 2 - V 1 ) R 1

Practical OP-AMP parameters OP-AMP characteristics DC characteristics AC characteristics  Input bias current Frequency responce  Input offset current Stability  Input offset voltage Frequency compensation  Thermal drift Slew rate

Input bias and offset currents  Input bias current I B is the average of the currents flowing into the two input terminals of the OP-AMP i.e. I B1 and I B2 are two currents then Input bias current I B = I B1 + I B2 2  The algebraic difference between the currents flowing into the inverting and non- inverting terminals of OP-AMP is called as “input offset current” I ios. I ios = │ I B1 - I B2 │  Ideally the value for both should be zero.  Practically it should be as low as possible.

Input and output offset voltages  The small differential voltage applied at the input of the OP-AMP to make the output zero is known as input offset voltage V ios.  Ideally it should be zero and practically as low as possible.  Total input offset voltage of OP-AMP, V ios (total) = V ios (initial) + T.C.(V ios )ΔT + ΔV 1 + ΔV + ΔVo CMRR PSRR A D where, V ios (initial) = Initial input offset voltage (at ambient voltage)  The output voltage produced due to input offset voltage is called as output offset voltage, V oos.  Total output offset voltage of OP-AMP, V oos = 1 + R F V ios + R F I B R 1  Where, I B is replaced by I ios,when R comp is connected with non-inverting amplifier.

Thermal drift  The thermal drift is defined as the average rate of change of input offset voltage per unit change in temperature and is denoted by Δ V ios / Δ T. It is expressed in μ V/ o C.  Thermal drift in the input offset current = Δ I ios / Δ T. It is expressed in p A/ o C and  Thermal drift in the input bias current = Δ I B / Δ T. It is expressed in p A/ o C.

Error voltage  Error voltage (E V ) can be defined as maximum possible change in V OOT. It can be calculated for non-inverting amplifier by following equation- E V = Δ V OOT = 1 + R F Δ V ios Δ T + R F Δ I ios Δ T R 1 Δ T Δ T  It can be negative or positive. Hence the expression for the output voltage of an invering amplifier is given by, V O = - R F V i ± E V R 1  Ideally it should be zero but in practice E V can’t reduced to zero.

Common mode rejection ratio (CMRR)  CMRR is the capability of OP-AMP to successfully reject the common mode signals.It is denoted by p and it is generally expressed in decibels (dB).  CMRR (dB) = 20 log 10 A CM A d  CMRR of a practical OP-AMP is not ∞. However it is very high. For IC 741, the CMRR is 90 dB or Such a high CMRR helps to reject the common mode signals such as noise, successfully.  In absence of input offset voltage, the OP-AMP should respond only to the differential input voltage V d. But a practical OP-AMP is sensitive to the common mode input V CM = (V 1 + V 2 ) 2  V o = A d V d + A CM V CM

Power supply rejection ratio (PSRR)  The change in an OP-AMP’s input offset voltage (V ios ) caused by variation in the supply voltage is called as power supply rejection ratio (PSRR).  It is also called as supply voltage rejection ratio (SVRR) or power supply sensitivity (PSS).Mathematically PSRR is expressed as : PSRR = Δ V ios Δ V  It is expressed either in microvolts per volt or in decibels.  For IC 741c, PSRR = 150 μ V/ V. The value of PSRR should ideally be equal to zero and practically it should be as small as possible.

Effect of variation in power supply voltage on offset voltage  The values of V ios, I ios, and I B are dependent on the variation in the power supply voltage (V CC and V EE ) as well.  For an OP-AMP, when the values of + V CC and – V EE are decided for a particular application, we do not change them deliberately. But due to poor filtering or poor regulation of power supplies, sometimes these voltages may change.  The variation in input bias current I B and input offset current I ios with change in supply voltage is shown in figures (a) and (b) respectively.

Change in input offset voltage, and input bias current with time  The last factor that affects the values of V ios and I B of an OP-AMP is time.  As OP-AMPs are made from diode and transistors, the input offset voltage and input bias current will vary with time. This will adversely affect the long term stability of an OP-AMP.  In data sheets of some OP-AMPs, the values of input bias current drift and input offset voltage drift with respect to time is specified. These drifts are denoted by Δ V ios / Δ t and Δ I B /Δ t.  The value of Δ V ios / Δ t is specified in microvolts per week and the value of Δ I B / Δ t is specified in nanometers per week.  The maximum change in the output offset voltage with respect to time is given by, V OOT = 1 + R F V ios Δ t + R F Δ I ios Δ t R 1 Δ t Δ t