CMOS AMPLIFIERS Simple Inverting Amplifier Differential Amplifiers Cascode Amplifier Output Amplifiers Summary

Simple Inverting Amplifiers

Small Signal Characteristics How do you get better matching? Inverter with diode connection load

High gain inverters

Current source load or push-pull Refer to book for large signal analysis Must match quiescent currents in PMOS and NMOS transistors Wider output swing, especially push-pull Much high gain (at DC), but much lower - 3dB frequency (vs diode load) About the same GB Very power dependent

Small signal High gain!

Key to analysis by hand: Use level 1 or 3 model equations Use KCL/KVL

Dependence of Gain upon Bias Current

Transfer function of a system System input uoutput y

When u(s) = 0, y(s) satisfies: These dynamics are the characteristic dynamics of the system. The roots of the coefficient polynomial are the poles of the system. When y(s) = 0, u(s) satisfies: These dynamics are the zero dynamics of the system. The roots of the coefficient polynomial are the zeros of the system.

Frequency Response of CMOS Inverters

Poles of CMOS Inverters Let vin = 0, x = 0, V DD = 0, V SS = 0. y C GS1, C GS2, C BS1, C BS2 are all short C GD1, C GD2, C BD1, C BD2, C L in parallel C’ L = C total = C GD1 + C GD2 + C BD1 + C BD2 + C L

Total conductance from y to ground: go = g ds1 + g ds2 KCL at node y: Therefore system pole is:

Zeros of CMOS Inverters Let vin = x = u, V DD = 0, V SS = 0. g ds1, g ds2 also short C GD1, C GD2, are in parallel, C BD1, C BD2, C L are all short No current in them KCL: Zero is:

Input output transfer function When s=j   0, A(0)  When w  ∞, A(s) 

|p 1 |= g0/CL’ |z 1 | =gm/Cgd =GB*CL’/Cgd A 0 =gm/go 0 dB Unity gain frequency =|A 0 p 1 | =GB =gm/CL’ Acl=1/  -3dB frequency of closed loop =  *GB

Unity gain feedback A(s)

If a step input is given, the output response is In the time domain: Final settling determined by A 0  need high gain Settling speed determined by A 0 p 1 =GB,  need high gain bandwidth product

Gain bandwidth product C’ L = C total = C GD1 + C GD2 + C BD1 + C BD2 + C L When C L ≈ C’ L, W↑  GB↑, but it saturates, when

Note: If V EB1 and V EB2 are fixed, W1/L1 and W2/L2 must be adjusted proportionally, and they are proportional to DC power.

Therefore: P is proportional to W1, W2 C L constant, but C(W 1,W 2 ) proportional to W1, W2 When C(W1, W2) << CL, GB proportional to P When C(W1,W2)  CL or >CL, GB saturates

P GB Linear increase region

NOISE IN MOS INVERTERS

For 1/f noise:

For thermal noise

Noise in Push-Pull current source load Inverter

Differential Input, single-ended output single stage Amplifier N-Channel v in+ v in-

P-channel

Large Signal Eq. in a N-channel Differential pair i D1 =0, when i D2 =I SS and V GS2 =V T +(2I SS /  ) 0.5 =0.5  1 (V GS1 -V T ) 2 =(2I D1 /  1 ) 0.5

Solving for i D1 and i D2 V ON1 =V ON2 =(I SS /  ) 0.5 i D1 =i D2 =I SS /2

N-Channel Input Pair Differential Amplifier C.M. Load C.M. Bias Simple current reference

Voltage transfer curve

P-Channel Input Pair Differential Amplifier

Voltage transfer curve

INPUT COMMON MODE RANGE V G1 =V G2 =V iCM V SDSAT1 =V SDSAT2 =V ON V D1 =V D3 = V SS +V T3 +V ON V G1min =V D1 -|V T1 | V G1max =V DD - V SD5SAT -|V T1 |-V ON

Output Range V omin =V ss +V on4 V omax =V icm –|V T2 | So what’s the vo range What’s for the N-ch circuit.

SMALL SIGNAL ANALYSIS AVAV

Common Mode Equivalent Circuit, with perfect match i C1 i C1 =V IC /(1/g m1 +2r ds5 ) r o1 ≈1/g m3 A CM ≈ 1/ 2r ds5 g m3 CMRR=A v /A CM =2g m1 g m3 /(g ds4 +g ds2 )/g ds5

If not perfectly matched i C1 i o =  i IC  is a fraction g o1 ≈ g ds2 + g ds4 A CM ≈  g ds5 / 2(g ds2 + g ds4 ) CMRR=A v /A CM =2g m1 /  g ds5

Formal detailed analysis

SLEW RATE: the limit of the rate of change of the output voltage Max |C L dv o /dt|=I SS C’ L dv o /dt=i 4 -i 2 Slew Rate = I SS /C’ L I SS 0 Output swing: V osw GB frequency: f GB v o (t)=V osw sin(2  f GB t) Max dv o /dt = V osw 2  f GB To avoid slewing: I SS > C’ L V osw 2  f GB

Parasitic Capacitances C T : common mode only C M : mirror cap = C dg1 + C db1 + C gs3 + C gs4 + C db3 C OUT = output cap = C bd4 + C bd2 + C gd2 + C L

Impedances –r out = r sd2 || r ds4 = 1 / (g ds2 + g ds4 ) –r M = 1/g m3 || r ds3 || r ds1 ≈ 1/ g m3 –Hence the output node is the high impedance node When v i =0, slowest discharging node is output node with dominant pole p 1 = -1/(C’ out r out ), where C’ out = C out + C gd4 Approximate transfer function A V (s) = A V /(s/p 1 ─1)

When v G1 =v G2 =0(AC) KCL at D1: KCL at D2:

Gain bandwidth product Gain A V (0) = g m1 / (g ds2 + g ds4 ) Bandwidth ≈ |p1| ≈ (g ds2 + g ds4 ) / C’ out GBW ≈ g m1 / C’ out g m1 = {2*I D1  C ox W1/L1} ½ – increase g m1  increase GBW – increase W1  increase GBW But C’ out has C db2 and C gd2  W1 –Once C db2 and C gd2 become comparable to C L, increasing W1 reduces GBW

Other poles and zeros M3M3 M2M2 M5M5 M1M1 M4M4 V b2 V DD V OUT CLCL Vi+ Vi- C gd4 (1+A V4 )C gd4 C gd4 Second pole at D 1 r = 1/g m3 C = C M + (1+A V4 )C gd4 p 2 = C M + (1+A V4 )C gd4 ─ g m3 A V4 = g m4 /g ds4

M3 M2 M5 M1 M4 V b2 V DD V OUT CLCL Vi+ = - Vi- Vi- Unstable zero at C gd2 Enforce v o =0, float v in. i ds2, i ds4 = 0 C gd2 dv i- /dt = g m2 v i- z1 = g m2 /C gd2

M3 M2M2 M5M5 M1 M4M4 V b2 V DD V OUT CLCL Vi+ Vi- For zero at D1: For diff, V i+ = - V i- which is set by C gd2  Both C gd4 and C gd1 to gnd C tot = C M + C gd4 z 2 = C M + C gd4 ─g m3

A better approximation of TF: A V (s)=A V (s/z 1 -1)(s/z 2 -1)/(s/p 1 -1)(s/p 2 -1) If p1 is dominant, |p1|<<|p2|,|z1|,|z2|; A V (s)≈A V /(s/p 1 -1) If p1 is non-dominant, at low frequency, A V (s)≈A V /(s/p 1 +s/p 2 -s/z 1 -s/z 2 -1) 1/p eq ≈ 1/p 1 +1/p 2 -1/z 1 -1/z 2 ≈ 1/p 1 +1/p 2 -1/z 2, since |z 1 | >> |z 2 |, |p 1 |, |p 2 |; ≈ 1/p 1, if A V4 is not very large In either case, BW ≈ p 1

frequency response AVAV PM p1p2z2 z1  UGF All in abs val

Observations PM ≈ 90 – tan -1 (UGF/z 1 )  GBW should be at least 2~3 times lower than z1 to ensure good phase margin at UGF  There is conflict between A V and PM If z 2 not = p 2, UGF < A V *p 1 Design approaches make z1 high  higher than UGF make Cgd2 small, gm1 large make z2 close to p2  better 1 st order approx. make A V4 small make p1 low  large A V make g ds2 and g ds4 small

Design Steps Select Iss based on –GB & V_osw, SR, or P_max Select W1/L1 based on –GB = gm/CL’, Assuming CL’ = (1.1~1.5)CL –Maximize z1 (minimize Cgd2) Select W4/L4 based on –ICMR, –Small Av4 Select W5/L5 based on –ICMR

NOISE Model

Input equivalent noise source

Total output noise current is found as, Let Then

How does this affect Av4 and go?

Cascoding Objectives –Increase r o –Increase A V –Remove feed forward from v in to v o –Remove unstable zero Methods –Direct cascoding –Folded cascoding

CMOS CASCODE AMPLIFIERS V DD  V bb V in CLCL RbRb V out-min increase by V ON2 Vout-max decreased if a Cascoded source used Output swing is a big Problem in low voltage Applications V DD  V in CLCL RbRb

  V bb V in CLCL   V yy V xx V DD Q: How should you set the bias? Q: what is V out-max ? r o = A V = r o at D1? v D1 v in = Cascoded current source load

  V bb V in CLCL   V yy V xx V DD High frequency model A V (s) = A V0 (s/z1 -1)… (s/p1-1)(s/p2-1)… For poles, short input, and compute the time constants at each node. For zeros, float input but require v o = 0. (don’t short v o !) Consider only the effect of the lower half circuit.

  V bb V in CLCL   V yy V xx V DD Short v in, float v o : At the high impedance node r =r ds1 (g m2 +g mb2 )r ds2 C =C L +C db2 +C gd2 p1 = -1/RC At the low impedance node r =1/( g m2 +g mb2 +g ds1 +g ds2 ) C =C gd1 +C db1 +C gs2 +C sb2 p2 =

  V bb V in CLCL   V yy V xx V DD Enforce v o =0, float v in. At the G1-D node  i Co =0, no current cross line, and i Cgd2 =0  id2, id3 = 0, g m2 v gs2 =0 Was the unstable zero removed? v s2 =0 i gds1 =0 sC gd1 v in =g m1 v in

Gain bandwidth product If |p 1 | << |p 2 |, |p 3 |,…, |p 1 | << |z 1 |, |z 2 |,… –BW ≈ |p 1 | –GBW ≈ g m1 /C o Otherwise –A V (s) ≈ A V /(s/p 1 +s/p 2 …-s/z 1 -s/z 2 … - 1) – 1/BW ≈ 1/p 1 +2/p 2 …-1/z 1 -2/z 2 … = RC 1 + RC 2 + …

V DD  V bb V in CLCL RbRb V DD Any enhancement? Note: r ds2, R b  1/I D2 g m2  √I D2 Effects on: r o, AV C o, GBW Slew rate

V DD  V bb V in CLCL RbRb Another possible modification Effects on: r o, AV? C o, GBW? Slew rate? poles? zeros?

V DD  V in CLCL Folded cascoding Which I source should be cascoded? r o, AV? C o, GBW? Slew rate? poles? zeros?  V bb

OUTPUT AMPLIFIERS Requirements –Provide sufficient output power in the form of voltage or current. –Avoid signal distortion for large signal swings. –Be power efficient. –Provide protection from abnormal conditions. Types of Output Stages –Class A amplifier. –Source follower. –Push-Pull amplifier ( inverting and follower). –Negative feedback (OP amp and resistive).

Power efficiency It is most power efficient at maximum signal level Let V SS = ─V DD, Vin is sinusoidal such that V out reaches V outmax P RL = ½ (V outmax ) 2 /R L P supply =average((V DD or V SS )*I RL ) =VDD*average(V outmax /RL *sin()) =2*VDD*V outmax /R L /  Power efficicy = P RL /P supply <  /4 (78%)

CLASS A AMPLIFIER r o, A V, z, p as before Power effic = P RL P supply = 0.5v outmax I Q I Q (V DD -V SS ) < 25% V SS =-V DD, V outmax =V DD -V dssat

SOURCE FOLLOWER or V SS +V T

Push-pull

Push-pull inverting amp

Implementation

PUSH-PULL SOURCE FOLLOWER

Negative Feedback To Reduce Rout R o =?

Super source follower V DD  V in  VoVo  V o =>  I 1 =(g m1 +g mb1 )  V o  V GS2 = r o1 (g m1 +g mb1 )  V o  I 2 = g m2 r o1 (g m1 +g mb1 )  V o I1 I2 g o =g m2 r o1 (g m1 +g mb1 ) +(g m1 +g mb1 )+g o2 ≈g m2 r o1 (g m1 +g mb1 ) G m ≈g m1 +g m1 r o1 g m2 A V =G m /g o ≈ g m1 g m1 + g mb1 Ex: rework these when I 1 and I 2 have finite r o s.

V DD  V in  VoVo I1 I2   If we re-arrange with a flipped version, we get this push-pull super source follower Ex: provide a transistor level implementation. Comment on power efficiency.