A U.S. Department of Energy Office of Science Laboratory Operated by The University of Chicago Argonne National Laboratory Office of Science U.S. Department.

Slides:



Advertisements
Similar presentations
Lecture 23: Registers and Counters (2)
Advertisements

Control path Recall that the control path is the physical entity in a processor which: fetches instructions, fetches operands, decodes instructions, schedules.
Programmable Interval Timer
Computer Science 210 Computer Organization Clocks and Memory Elements.
Storey: Electrical & Electronic Systems © Pearson Education Limited 2004 OHT 10.1 Sequential Logic  Introduction  Bistables  Memory Registers  Shift.
Flip-Flops, Registers, Counters, and a Simple Processor
Counter Circuits and VHDL State Machines
EE42/100 Fall 2005 Prof. Fearing 1 Week 12/ Lecture 22 Nov. 17, Overview of Digital Systems 2.CMOS Inverter 3.CMOS Gates 4.Digital Logic 5.Combinational.
CS 300 – Lecture 3 Intro to Computer Architecture / Assembly Language Sequential Circuits.
Homework Reading Machine Projects Labs Tokheim Chapter 9.1 – 9.6
Computerized Train Control System by: Shawn Lord Christian Thompson Advisor: Dr. Schertz.
A U.S. Department of Energy Office of Science Laboratory Operated by The University of Chicago Argonne National Laboratory Office of Science U.S. Department.
Fundamentals of Digital Logic B. Furman 25NOV2014.
Fall 2007 L16: Memory Elements LECTURE 16: Clocks Sequential circuit design The basic memory element: a latch Flip Flops.
Chapter 7 – Registers and Register Transfers Part 1 – Registers, Microoperations and Implementations Logic and Computer Design Fundamentals.
Sequential Circuit  It is a type of logic circuit whose output depends not only on the present value of its input signals but on the past history of its.
Microprocessor and Microcontroller Based Systems Instructor: Eng.Moayed N. EL Mobaied The Islamic University of Gaza Faculty of Engineering Electrical.
A U.S. Department of Energy Office of Science Laboratory Operated by The University of Chicago Argonne National Laboratory Office of Science U.S. Department.
Introduction to Counter in VHDL
ENGSCI 232 Computer Systems Lecture 5: Synchronous Circuits.
Micro-operations Are the functional, or atomic, operations of a processor. A single micro-operation generally involves a transfer between registers, transfer.
8254 Programmable Interval Timer
ARM Timers.
APS BPM and power supply applications on micro-IOCs W. Eric Norum
The 8253 Programmable Interval Timer
School of Computer Science G51CSA 1 Computer Systems Architecture Fundamentals Of Digital Logic.
Computer Design Basics
A U.S. Department of Energy Office of Science Laboratory Operated by The University of Chicago Argonne National Laboratory Office of Science U.S. Department.
A U.S. Department of Energy Office of Science Laboratory Operated by The University of Chicago Argonne National Laboratory Office of Science U.S. Department.
A U.S. Department of Energy Office of Science Laboratory Operated by The University of Chicago Argonne National Laboratory Office of Science U.S. Department.
Senior Project Presentation: Designers: Shreya Prasad & Heather Smith Advisor: Dr. Vinod Prasad May 6th, 2003 Internal Hardware Design of a Microcontroller.
SEQUENTIAL CIRCUITS Component Design and Use. Register with Parallel Load  Register: Group of Flip-Flops  Ex: D Flip-Flops  Holds a Word of Data 
Basic Sequential Components CT101 – Computing Systems Organization.
Chap 7. Register Transfers and Datapaths. 7.1 Datapaths and Operations Two types of modules of digital systems –Datapath perform data-processing operations.
REGISTER TRANSFER & MICROOPERATIONS By Sohaib. Digital System Overview  Each module is built from digital components  Registers  Decoders  Arithmetic.
CascadedBCDCntr&Display Aim : Capture, simulate and implement a 2-digit, loadable BCD up/down counter, with chip enable I/P (CE) and chip enable O/P (CEO).
Anurag Dwivedi. Basic Block - Gates Gates -> Flip Flops.
Introduction to VHDL Simulation … Synthesis …. The digital design process… Initial specification Block diagram Final product Circuit equations Logic design.
Computer Hardware A computer is made of internal components Central Processor Unit Internal External and external components.
IT253: Computer Organization Lecture 9: Making a Processor: Single-Cycle Processor Design Tonga Institute of Higher Education.
Computer Architecture and Organization Unit -1. Digital Logic Circuits – Logic Gates – Boolean Algebra – Map Simplification – Combinational Circuits –
Registers 4.2 N-bit register: Stores N bits, N is the width
June 9, s Massachusetts Institute of Technology 6.11s: Design of Motors, Generators and Drive Systems Switching Patterns and Simple Implementation.
Logic Design / Processor and Control Units Tony Diep.
Digital Electronics and Computer Interfacing Tim Mewes 5. Computer Interfacing – DAQ cards.
COUNTERS Why do we need counters?
Chapter 6 – Digital Electronics – Part 1 1.D (Data) Flip Flops 2.RS (Set-Reset) Flip Flops 3.T Flip Flops 4.JK Flip Flops 5.JKMS Flip Flops Information.
CS151 Introduction to Digital Design Chapter 3: Combinational Logic Design 3-5 Combinational Functional Blocks 3-6 Rudimentary Logic Functions 3-7 Decoding.
#1 of 10 Tutorial Introduction PURPOSE -To explain how to configure and use the Timer Interface Module in common applications OBJECTIVES: -Identify the.
Chap 5. Registers and Counters
1 KU College of Engineering Elec 204: Digital Systems Design Lecture 23 Introduction Computer Specification –Instruction Set Architecture (ISA) - the specification.
Processor Organization and Architecture Module III.
Chapter 3. Advanced Hardware Fundamentals The various parts you will commonly find in an embedded-system circuit 발표일시 : 발표자 : 채화영.
Counters and registers Eng.Maha Alqubali. Registers Registers are groups of flip-flops, where each flip- flop is capable of storing one bit of information.
Module 8 Tutorial  An 8086 system is used for controlling the speed of a motor. The motor can operate at 5 different speeds (1- 5).  The speed.
Sequential Logic Design
Computer Science 210 Computer Organization
Class Exercise 1B.
Basic Computer Organization and Design
Digital Electronics Multiplexer
KU College of Engineering Elec 204: Digital Systems Design
Digital Electronics Multiplexer
Computer Science 210 Computer Organization
Latches and Flip-flops
COSC 2021: Computer Organization Instructor: Dr. Amir Asif
Computer Science 210 Computer Organization
COE 202: Digital Logic Design Sequential Circuits Part 4
Computer Architecture and Organization: L02: Logic design Review
Overview Part 1 - Registers, Microoperations and Implementations
Sequential Logic.
Presentation transcript:

A U.S. Department of Energy Office of Science Laboratory Operated by The University of Chicago Argonne National Laboratory Office of Science U.S. Department of Energy softGlue Run-time programmable digital electronics Tim Mooney May, 2015 This work is supported by the U.S. Department of Energy, Basic Energy Sciences, Office of Science, under contract DE-AC02-06CH11357.

softGlue Pioneering Science and Technology Office of Science U.S. Department of Energy Overview SoftGlue enables beamline users and staff to construct simple digital electronic circuits, and connect those circuits to field wiring, by writing to EPICS process variables (PVs). SoftGlue also provides safe (throttled) user control over how hardware interrupts are generated by field I/O signals, and dispatched to cause EPICS processing. SoftGlue circuits can be autosaved and restored, saved as text files, ed to another user, and managed by configMenu. SoftGlue does this by loading an IndustryPack FPGA-based digital I/O module with a predefined collection of circuit elements (logic gates, counters, flip-flops, etc.), whose inputs and outputs are connected to switches controlled by EPICS PVs.

softGlue Pioneering Science and Technology Office of Science U.S. Department of Energy MEDM display

softGlue Pioneering Science and Technology Office of Science U.S. Department of Energy How it works, conceptually

softGlue Pioneering Science and Technology Office of Science U.S. Department of Energy Circuit-element inputs optionexampleresultcomment empty1 number1 0 1! 0! Positive-going pulse Negative-going pulse 0 ~6  s namemySignalConnected to all other inputs and output named “mySignal”

softGlue Pioneering Science and Technology Office of Science U.S. Department of Energy Additional circuit elements Quadrature decoder read encoder Up/Dn Counter count output signals from quadrature decoder Shift register bit stream I/O Other circuit elements are possible. See Kurt Goetze.

softGlue Pioneering Science and Technology Office of Science U.S. Department of Energy Example applications With no user programming, softGlue is a digital I/O module. Trigger a detector after every N steps of a motor. Trigger a detector after every N[i] steps of an encoder. Gate a detector off during a motor’s accel/decel time. Trigger a detector 23.7 ms after a shutter. Conditionally execute an EPICS record on the rising edge of an external signal. Implement an extraordinarily smart oscilloscope trigger. Cause an EPICS database to wait for 0.7 ms. Count encoder pulses. Convert encoder pulses to up/down pulses, for use with a multichannel scaler. Send/receive a bit stream from external hardware. Latch the value of an external signal.

softGlue Pioneering Science and Technology Office of Science U.S. Department of Energy Documented example circuits -Programmable pulse trainProgrammable pulse train -Gated scalerGated scaler -Pulse burstPulse burst -Delay generatorDelay generator -Motor accel/decel pulse gateMotor accel/decel pulse gate -DebouncerDebouncer -TTL Pulse Stretcher and DelayTTL Pulse Stretcher and Delay

softGlue Pioneering Science and Technology Office of Science U.S. Department of Energy Field I/O Connected just as are circuit elements Interrupt can drive EPICS record on falling edge, rising edge, etc.

softGlue Pioneering Science and Technology Office of Science U.S. Department of Energy Field I/O cable termination A: 100-Ohm series termination to ribbon cables B: 50-Ohm line driver for RG58/RG174 coaxial cables AB

softGlue Pioneering Science and Technology Office of Science U.S. Department of Energy since last softGlue talk (Kurt Goetze) Support for IP_EP20x (RS-422, lvds) Field I/O cable termination strategy Shift registers, quadrature decoders, up/down counters Divide-By-N's RESET signal now works Displays for caQtDM and CSS-BOY configMenu support for saving and restoring circuits -requires autosave R5-1 Circuit, component descriptions Build is no longer restricted to vxWorks Support for registering and calling a custom interrupt handler Support for calculating the VME address of a softGlue register caputRecorder macro to move/copy a component from one softGlue instance to another Build is no longer restricted to vxWorks

softGlue Pioneering Science and Technology Office of Science U.S. Department of Energy since last softGlue talk (Kurt Goetze) Support for IP_EP20x (RS-422, lvds) Field I/O cable termination strategy Shift registers, quadrature decoders, up/down counters Divide-By-N's RESET signal now works Displays for caQtDM and CSS-BOY configMenu support for saving and restoring circuits -requires autosave R5-1 Circuit, component descriptions Build is no longer restricted to vxWorks Support for registering and calling a custom interrupt handler Support for calculating the VME address of a softGlue register caputRecorder macro to move/copy a component from one softGlue instance to another

softGlue Pioneering Science and Technology Office of Science U.S. Department of Energy softGlue: credits Eric Norum – IndustryPack Bridge -interfaces FPGA components to IP/VME bus Marty Smith –EPICS driver, FPGA content for field I/O Kurt Goetze – FPGA content for softGlue, custom hardware Tim Mooney – softGlue driver, EPICS application