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The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. Stamatis Vassiliadis Symposium Future Research in Computer Arithmetic September 28, 2007 Eric Schwarz, IBM

Stamatis Vassiliadis Symposium Topics »Binary Multiplication Proofs of Overlapped ScanningFoundations 7:3 Counter DesignFuture »Division Direct Division Remainder Avoidanceactive »Decimal Floating-Point extremely active Pipelining Add Multiply Multiply-Add

Binary Multiplication

Stamatis Vassiliadis Symposium Basics »Recode multiplier and separate into digits »Create multiples of the multiplicand »Multiplex the multiples »Sum all partial products in counter tree »reduce final 2 partial products in CLA

Stamatis Vassiliadis Symposium History of Overlapped Scanning »A.D. Booth in 1951 showed overlapped scanning »L. Rubinfield in 1975 proved radix-4 Booth »S. Vassiliadis in 1989 proved Booth for any radix

Stamatis Vassiliadis Symposium Fixed Point Multiplication in 1973

Stamatis Vassiliadis Symposium Fixed Point Multiplication in 1991

Stamatis Vassiliadis Symposium High Level Counters 7:3 US Patent 5,187,679 in 1993

Power6 and Z6* Decimal Floating Point: Hardware

Stamatis Vassiliadis Symposium Power6 and Z6* processors have DFU Core Core L2Ctrl L2Ctrl L2DataL2Data L2DataL2Data L3Ctrl L3Ctrl MemCtrlMemCtrl

Stamatis Vassiliadis Symposium 754R Decimal Floating Point Format »IEEE 754R defines 2 formats: Integer coefficient & DPD (Densely Packed Decimal) »Formats for 32,64,128 bit. C encodes 2 exponent bits and 1 decimal digit in 5 bits. decimal32decimal64decimal128 Coefficient precision (p) Bits of Exponent Exponent range-101 to to to 6111 Nmax( ) x ( ) x ( ) x Nmin1 x x x S1S1 C5C5 Exp 6,8,12 Coef 20,50,110

Stamatis Vassiliadis Symposium Power6 Decimal Floating Point Unit »Cycle Time: approx 5Ghz, 13 FO4 design »Hardware executes 64-bit and 128-bit formats. 144-bit Dataflow can be split into two 72-bit pipes. DPD coefficients are decoded into BCD for execution. »All cases are handled in hardware. (No Special Case Software Traps)

Stamatis Vassiliadis Symposium Coefficient Dataflow Compress BCD to DPD Operand B Hi Register Operand A Hi Register Operand B Lo Register Operand A Lo Register Expand DPD to BCD Working Register HiWorking Register Lo Result Register Hi Result Register Lo Multiple Generator 36 digits wide (144 bits) Pipelined 2 cycle Rotator 4D 2D 4D +1 Adder Register 2D Doubler & Quintupler 1X,3X,4X Registers A muxB mux Q Prescale Table Q Correction and Multiplexers DEC to BIN & BIN to DEC Converters Q 36 Digit Dataflow splits to Two 18 Digit Dataflows Magnitude Calculations: A-BB-A Multiplication:Partial Product AccumulateGenerate

Stamatis Vassiliadis Symposium Power6 DFP Multiplication Partial products are formed from two multiples to reduce area MultipleAB 1X0 2X 0 3X2X1X 4X2X 5X 0 6X5X1X 7X5X2X 8X10X-2X 9X10X-1X 34 digit multiplication on 36 digit dataflow 1 digit every 2 cycles: 16 digit multiplication on dual 18 digit dataflows 1 digit every cycles:

Stamatis Vassiliadis Symposium Performance of Arithemetic Operations Cycles Required for Execution Doubleword OperandsQuadword Operands Case 1 Add/Sub9 to 1311 to 15 Case 2 Add/Sub11 to 1513 to 17 Case 3 Add/Sub13 to 1715 to 19 Multiplication * 19 + N21 + 2N Division82154 * N is the number of digits in the first operand excluding leading zeros

Stamatis Vassiliadis Symposium Future »Pipelined Adder with Rounding Injection Lia-Kai Wang »Decimal Multiplication Mark Erle and Michael Schulte – 3:2 Counter Tomas Lang and A. Nannarelli- 4:2 Counter Alvaro Vazquez et. al Luigi Dadda - counters »Decimal Multiply-Add Pipeline with Rounding Injection »Divide Tomas Lang and A. Nannarelli – Base 2 and Base 5 »Intel Format

Stamatis Vassiliadis Symposium Future of Computer Arithmetic »Is based on clear proofs and expositions of the fundamental concepts. the easier to understand, the easier to build on »Arithmetic is very active IEEE 754R Standard currently in ballot Decimal Floating-Point pipelined designs new adder designs, new multiplier designs vector processing, image processing, video game

Stamatis Vassiliadis Symposium thanks Stamatis!

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