1. CS/CoE 536 : Lockwood 1 CS/CoE 536 Reconfigurable System On Chip Design Lecture 10 : MP3 Working Draft Washington University Fall 2002 http://www.arl.wustl.edu/~lockwood/class/cs536/ John Lockwood Copyright 2002 Lockwood@arl.wustl.edu

2. CS/CoE 536 : Lockwood 2 Overall CS536 Machine Problem Structures Layered Protocol Wrappers Content- based Match (regex) (MP2) CAM-based Firewall (MP1 w/extra entries & FlowID) Flow Buffer Queue Manager (MP3) Input Traffic From Linecard Firewall on a Chip ( Implemented on the RAD on the FPX, a VirtexE 2000 FPGA ) Output Traffic To Linecard or switch p p p p Off-Chip Synchronous Random Access Memory (SDRAM) Match vector Flow# from CAM Identify packets Based on Head Pointers Tail Pointers SDRAM Free List Manager SDRAM Free pointers 16 Off-Chip Static Random Access Memory (SRAM) SRAM Controller SDRAM Controller SRAM Interface Sche- duler 16

3. CS/CoE 536 : Lockwood 3 Signal Interface of Flow Buffer --A. packet data going to the flow buffer PktDataIn : in std_logic_vector(31 downto 0); PktDataInValid : in std_logic; SoPktIn : in std_logic; EoPktIn : in std_logic; --B. packet data going out of the flow buffer PktDataOut : out std_logic_vector(31 downto 0); PktDataOutValid : out std_logic; SoPktOut : out std_logic; EoPktOut : out std_logic; --C. Interface with the Queue Context ---The following two signals come from the QueueContext Tail : in std_logic_vector(31 downto 0);; TailValid : in std_logic; ---The following two signals go to the queue context NextTail : out std_logic_vector(31 downto 0);; NextTailValid : out std_logic; ---The following two signals come from the QueueContext Head : in std_logic_vector(31 downto 0);; HeadValid : in std_logic; ---The following two signals go to the queue context NextHead : out std_logic_vector(31 downto 0);; NextHeadValid : out std_logic; Flow Buffer Queue Manager (MP 3) pp A. B. C. Queue Selector (MP 1) Queue Scheduler (MP 3)

4. CS/CoE 536 : Lockwood 4 Using the ZBT SRAM Controller SRAM_REQ –Request to use Interface SRAM_GR –Grant to use interface SRAM_D_IN –Data Bus to module from SRAM (36 bits) SRAM_D_OUT –Data Bus from module to SRAM (36 bits) SRAM_ADDR –Address (18 bits provide access to 256k words) SRAM_WR_RD –Write=0, Read=1 SRAM_D_OUT[35:0] SRAM_ADDR[17:0] SRAM_WR_RD SRAM_REQ SRAM_GR SRAM_D_IN[35:0] SRAM Interface Off-Chip Static Random Access Memory (SRAM)

5. CS/CoE 536 : Lockwood 5 MP3 Assignment To Do List CAM –Provide 4 CAMs (from 2) –Add 16-bit entry called “Flow ID” to each CAM Provide output called FlowID from the CAM module Provide priority encoder so that the lower number CAM provides a value when multiple CAMs match –Add 16-bit entry called “Flow Hash” XORs bits in the header fields to produce a pseudo- unique flow identifier for each of the possible 2^112 Bits available to the CAM –Increase Number of data buffers Make sure that Flow_ID and Flow_Hash are valid when output is the start of the packet

6. CS/CoE 536 : Lockwood 6 Control Packet Updates Control Packet Update –Provide ability to update any CAM number, not just the first two –Add “No Transmit” and “Transmit” Control Bit (extra bit in header) Corresponds to Transmit_enable signal to QM When set, stops the QM from transmitting data. I.e., All data stays in the queue. I.e., Turn off the output I.e., Set C=0

7. CS/CoE 536 : Lockwood 7 MP3 CAM Datagram MP3 UDP Control Packet programs up-to-N CAM entries Fields allocated for: Transmit enable Base CAM Number of CAMs FlowID per CAM ATM Header Packet Len Source IP address 192.168.30.13 ( 0xC0A81E0D ) CAM_1_SRC_IP CAM_MASK_1 … (if necessary) ToSHLVer FragmentIP ID Src Port Dest Port ( 0x0320 ) LengthChecksum #CAMs AAL5 Pad CPS-UU & CPI AAL5 Frame Checksum Frame Len CAM_1_DEST_IP CAM_1_PORTS CAM_2_SRC_IP CAM_MASK_2 CAM_2_DEST_IP CAM_2_PORTS CAM_VALUE_1 CAM_MASK_1 CAM_VALUE_2 CAM_MASK_2 ChecksumProtoTTL Base_CAMX CAM_1_ PROTO (PAD) Match_ vector... CAM_2_ PROTO (PAD) Match_ vector Flow_ID transmit_enable

8. CS/CoE 536 : Lockwood 8 Other Issues SRAM Flows –Initialize values to i for i=0..64k