1. CS/CoE 536 : Lockwood 1 CS/CoE 536 Reconfigurable System On Chip Design Lecture 9 : MP3 Working Draft Washington University Fall 2002 http://www.arl.wustl.edu/~lockwood/class/cs536/ John Lockwood Copyright 2002 Lockwood@arl.wustl.edu

2. CS/CoE 536 : Lockwood 2 Overall CS536 Machine Problem Structures Layered Protocol Wrappers Content- based Match (regex) (MP2) CAM-based Firewall (MP1) Flow Buffer Queue Manager (MP 3) Input Traffic From Linecard Firewall on a Chip ( Boundry of the RAD on the FPX, a VirtexE 2000 FPGA ) Output Traffic To Linecard or switch p ppp Off-Chip Synchronous Random Access Memory (SDRAM) Match vector Flow# from CAM Free List Manager Identify packets Based on Head.PtrTail.Ptr Free.Ptr 16 Off-Chip Static Random Access Memory (SRAM)

3. CS/CoE 536 : Lockwood 3 Extension to CAM Lookup Filter Number of CAM entries –Expanded to 4 entries Additional Field in CAM –FlowID returns Additional Field in Control Packet –FlowID –Now 128 bits Priority Encoder –Output from the CAM has the FlowID from the lowest matching CAM entry.

4. CS/CoE 536 : Lockwood 4 Interface to Flow Buffer Signal Description --packet data going to the flow buffer PktDataIn : in std_logic_vector(31 downto 0); PktDataInValid : in std_logic; SoPktIn : in std_logic; EoPktIn : in std_logic; --packet data going out of the flow buffer PktDataOut : in std_logic_vector(31 downto 0); PktDataOutValid : in std_logic; SoPktOut : in std_logic; EoPktOut : in std_logic; --Interface with the Queue Contex ---The following two signals come from the QueueContext Tail : in std_logic_vector(31 downto 0);; TailValid : in std_logic; ---The following two signals go to the queue context NextTail : out std_logic_vector(31 downto 0);; NextTailValid : out std_logic; ---The following two signals come from the QueueContext Head : in std_logic_vector(31 downto 0);; HeadValid : in std_logic; ---The following two signals go to the queue context NextHead : out std_logic_vector(31 downto 0);; NextHeadValid : out std_logic;

5. CS/CoE 536 : Lockwood 5 `

6. 6 Interface to Flow Buffer Protocol

7. CS/CoE 536 : Lockwood 7 Interface to Flow Buffer Timing Diagram Example

8. CS/CoE 536 : Lockwood 8 RAD Module Interface Cell I/O and Flow Control –32-bit wide UTOPIA-style interface w/ unique timing Off-chip Memory Access –Arbitrated access to SRAM and SDRAM via standard interface Control (clock, reset, and reconfiguration control)

9. CS/CoE 536 : Lockwood 9 SRAM Interface Module Interface to off-chip ZBT SRAM Abstracts modules from device specific timing Independent interface for each module Arbitrates requests and issues grant to winning module Modules retain access by holding request high after receiving grant –Modules responsible for preventing starvation

10. CS/CoE 536 : Lockwood 10 SRAM Interface Timing All I/O signals must be flopped at module boundary to ensure timing constraints are met Timing diagrams take reference point from inside module and assume boundary flops

11. CS/CoE 536 : Lockwood 11 Design Issues & Recommendations Conform to the Module Interface Specification –Make your design as easy to integrate as possible Use provided infrastructure –Enables resources on the FPGA to be shared Use Synchronous Design Techniques –Flop all module I/O signals –Use synchronous reset Simulate Design –Verify that the device Synthesize Design –Over-constrain timing delays –Optimize along the critical path of the circuit Share experience and wisdom with other developers

12. CS/CoE 536 : Lockwood 12 Queue Management A B C Reserved Empty Slot [implementation dependant] M[x] M[y] M[z] M[u] Other Flow State FiFi Head Pointer D M[v] Note that packets can be stored anywhere in memory Packet Store Flow State Head Pointer Tail Pointer Empty Slot Head Pointer Tail Pointer Packet Reads = 3 FiFi Packet Writes = 3

13. CS/CoE 536 : Lockwood 13 Initial State of Queue Reserved Empty Slot [implementation dependant] M[0] F1F1 F0F0 Head Pointer M[64k] Note that packets can be stored anywhere in memory Packet Store Flow State Head Pointer Tail Pointer Empty Slots Head Pointer Tail Pointer Packet Reads = 3 FiFi Packet Writes = 3 Reserved Empty Slot [implementation dependant] M[1]

14. CS/CoE 536 : Lockwood 14 New Packet Arrives A B C New Data Reserved Empty Slot [implementation dependant] M[u] FiFi Packet Store Flow State Head Pointer Tail Pointer Empty Slot Updated Pointers Head Pointer Tail Pointer Packet Reads = 3 Packet Writes = 3

15. CS/CoE 536 : Lockwood 15 Packet Departs Head Pointer Tail Pointer Packet Reads = 3 B C FiFi Note that packets can be stored anywhere in memory Packet Store Flow State Head Pointer Tail Pointer Empty Slot Packet Writes = 3

16. CS/CoE 536 : Lockwood 16 2: Queue Manager provides an address Memory pointer, x = Flow[i].tail Detailed Operation of the Flow Buffer Flow Buffer Queue Manager pp Off-Chip Synchronous Random Access Memory (SDRAM) Free List Manager Tail.PtrHead.Ptr Free.Ptr 1: New packet data arrives on Flow Number i Packet Data Flow# Packet Data 5: Queue Manager provided with new memory pointer, y. Set Flow[i].tail = y 4: New memory pointer, y, provided from free list 1: QM Decides it is time for a packet to depart. Reads Flow[i].head = z 2: packet from M[z] 3: Packet Data stored in M[x] 3: QM sets Flow[I].head = M[z].next 5: z returned to the Free List 4: M[z].data transmitted

17. CS/CoE 536 : Lockwood 17 LNE HE EMPTY L H A aa 12n aaa 1 n service queues traffic vector of 3DQ : destination group (for outport n) destination group (for outport 1) per-VC queues VC W VCy HEAD tail (cell room available) freelist ATM cell in cell room free cell room NE A j j LEVEL priority VC X multicast VC non-empty unicast VC VC.. linked list pointers VC table 3DQ Architecture Traffic groups –Can avoids HOL blocking Prioritized Service Queues –N Priority levels (4) –Highest priority first Per-flow Queues –Linked list –Multicast

18. CS/CoE 536 : Lockwood 18 VCwVCxVCyVCwVCxVCy HEAD tail head VC W VCxVCy tailhead VC LINKTO service queue removed VC re-enters link to VC removed (b) an non-SQR case (a) a service queue(c) a SQR case per-VC queue service queue: Queue Re-entry Mechanism –VC queue re-enters service queue when the VC queue is not empty –SQR Statistically and Fairly Allocates Bandwidth to VCs That Belong to the Same Service Queue.

19. CS/CoE 536 : Lockwood 19 DiffServ Topology At the Edge of network –Uses only a few bits of information per packet –Typically marked by a Packet Classifier Cannot trust end users to mark their own packets –Everyone would want their packets to be most important! –Berkeley Unix defaults to using high priority Cannot usually trust other networks Ingress Router (Classify) Interior Router Egress Router Interior Router Egress Router Source Host Destination Host Ingress Router (Classify) Autonomous System 1 Autonomous System 2

20. CS/CoE 536 : Lockwood 20 Acknowledgements This presentation mentions: –DiffServ material Van Jacobson, Differentiated Services for the Internet, First Internet2 Joint Applications/Engineering QoS Workshop, May 21-22, 1998 –IntServ / DiffServ material http://www.cs.unc.edu/Courses/comp249- s02/lectures/comp249_s02_17/ –Hardware Queuing Design H. Duan, J. W. Lockwood, S. M. Kang, J.D. Will, A High- performance OC-12/OC-48 Queue Design Prototype for Input- buffered ATM Switches, IEEE Infocom '97, Kobe, Japan, April 7-11, 1997, pp 20-28.

21. CS/CoE 536 : Lockwood 21 MP3 Assignment To Do List CAM –Provide 4 CAMs (from 2) –Add 16-bit entry called “Flow ID” to each CAM Provide output called FlowID from the CAM module Provide priority encoder so that the lower number CAM provides a value when multiple CAMs match –Add 16-bit entry called “Flow Hash” XORs bits in the header fields to produce a pseudo- unique flow identifier for each of the possible 2^112 Bits available to the CAM SRAM Flows –Initialize values to i for i=0..64k –

22. CS/CoE 536 : Lockwood 22 MP3 Laboratory Todo Coregen “tutorial” –Just a few screen shots that show Creation of a FIFO Instantiation of a FIFO Simulation of FIFO –We will demonstrate this in class on Monday PPT slides with screen dumps

23. CS/CoE 536 : Lockwood 23 Control Packet Update –Provide ability to update any CAM number, not just the first two –Add “No Transmit” and “Transmit” Control Bit (extra bit in header) Corresponds to Transmit_enable signal to QM When set, stops the QM from transmitting data. I.e., All data stays in the queue. I.e., Turn off the output I.e., Set C=0