1. LECTURE V TEST BENCHES

2. As your projects become more complex and multiple modules are employed, it will no longer be possible to simulate them as we did in lecture IV. We will need to build" test benches". Test benches are modules which instantiate other module(s) and provide stimulus (inputs) and timing requirements to those modules. Consider the following example shown on pg 114, fig 3.2, a circuit with state propagation delays. // Verilog model of simple circuit with propagation delays module Simple_Circuuit_prop_delay (A,B,C,D,E); output D,E; input A,B,C; wire w1; and #(30) G1 (w1, A, B); not #(10) G2 (E,C); or #(20) G3 (D, w1, E); endmodule

3. //Test bench for Simple_Circuit_prop_delay module tb_Simple_Circuit_prop_delay; wire D,E; // keyword 'wire' is used to define outputs in test benches reg A,B,C; // keyword 'reg' is used to define inputs in test benches Simple_Circuit_prop_delay M1 (A,B,C,D,E); // Instance name (M1) required initial begin A = 1'b0; B = 1'b0; C = 1'b0; //note the individual semicolons used #100 A = 1'b1; B = 1'b1; C = 1'b1; // "#100" is 100 time units later in the simulation end initial #200 $stop; // Use stop instead of finish. Indicates the end of simulation endmodule

4. Note: every instantiation of a module requires a unique identifier, e.g. M1, M2, M3, etc. placed immediately after the modules name. The TB keyword initial is used to indicate instructions sent directly to the simulator. If the TB keywords begin and end are used after the TB keyword initial, the instructions included between them are executed sequentially, Left to Right, Top to Bottom. This list of statements is known as a "block statement". As mentioned above I suggest using the TB keyword $stop rather than $finish as $finish will kick you out of the simulation, probably before you are ready to leave it. The initial #200 $stop; line tells the simulator to stop executing 200 time at 200 time units past the starting point. Note: Instruction listed between a begin and end are indeed executed sequentially, but the entire test bench module is executed simultaneously. So, for example, if you had written the initial #200 $stop; as initial #50 $stop, the module would never have gotten to the #100 A = 1'b1; B = 1'b1; C = 1b'1; line. The simulation would have ended at 50 time units.

6. BOOLEAN EXPRESSIONS Defining Boolean expressions requires the use of the keyword "assign” along with specific symbols used to represent the various logic operators. To wit: To indicate an AND gate, use && To indicate an OR gate, use || To indicate a NOT gate, use ! For example the Boolean expression: E= A + BC + B'D becomes: assign E= A || (B&&C) + (!B&&D); in Verilog speak. Likewise, F= B'C + BC'D' becomes: assign F= (!B&&C) || (B&&(!C)&&(!D)); Note: Notice that the ! comes before the variable name as opposed to the ' coming after the variable name when expressed in Boolean form. e.g. !D as opposed to D' Also, a very common error when writing complex Boolean expressions is to forget an ")" or two. A good idea is to count the left "("s and the right ")"s and make sure that you have an equal number of both.