1. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust © 2008 Pearson Education Chapter 5 & 6

2. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed In this lecture we cover: 5-5 Logic Circuit Operation with Pulse Waveform Inputs 6-1 Basic Adders 6-2 Parallel Binary Adders

3. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pulsed Waveforms For combinational circuits with pulsed inputs, the output can be predicted by developing intermediate outputs and combining the result. For example, the circuit shown can be analyzed at the outputs of the OR gates: A B C D A B C D G1G1 G2G2 G3G3 G1G1 G2G2 G3G3

4. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pulsed Waveforms Alternatively, you can develop the truth table for the circuit and enter 0’s and 1’s on the waveforms. Then read the output from the table. A B C D A B C D G1G1 G2G2 G3G3 G3G3 Inputs A B C D Output 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 1 0 X 0 1 1 1 0 1 1 1 0 0 0 0 0 1 1 1

5. Universal gate Negative-OR Negative-AND Either a NAND or a NOR gate. The term universal refers to a property of a gate that permits any logic function to be implemented by that gate or by a combination of gates of that kind. The dual operation of a NAND gate when the inputs are active- LOW. The dual operation of a NOR gate when the inputs are active-LOW.

6. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Basic rules of binary addition are performed by a half adder, which has two binary inputs (A and B) and two binary outputs (Carry out and Sum). Half-Adder The inputs and outputs can be summarized on a truth table. A B  C out The logic symbol and equivalent circuit are: A B  C out 

7. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Full-Adder By contrast, a full adder has three binary inputs (A, B, and Carry in) and two binary outputs (Carry out and Sum). The truth table summarizes the operation. A full-adder can be constructed from two half adders as shown: A B  C out  A B   A B Sum C out C in A B  C out  C in Symbol

8. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Full-Adder A B  C out  A B   For the given inputs, determine the intermediate and final outputs of the full adder. 1 1 0 1 0 The first half-adder has inputs of 1 and 0; therefore the Sum =1 and the Carry out = 0. The second half-adder has inputs of 1 and 1; therefore the Sum = 0 and the Carry out = 1. The OR gate has inputs of 1 and 0, therefore the final carry out = 1. 1 0 1 Sum C out

9. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Full-Adder A B  C out  A B   1 1 0 1 0 1 0 1 Sum C out Notice that the result from the previous example can be read directly on the truth table for a full adder.

10. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Parallel Adders Full adders are combined into parallel adders that can add binary numbers with multiple bits. A 4-bit adder is shown. AB  C out C in AB  C out C in AB  C out C in AB  C out C in A 1 B 1  C0C0    C1C1 C2C2 C3C3 C4C4 A 2 B 2 A 3 B 3 A 4 B 4 The output carry (C 4 ) is not ready until it propagates through all of the full adders. This is called ripple carry, delaying the addition process.

11. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Parallel Adders The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder includes a carry in (labeled (C 0 ) and a Carry out (labeled C 4 ). The 74LS283 is an example. It features look-ahead carry, which adds logic to minimize the output carry delay. For the 74LS283, the maximum delay to the output carry is 17 ns. Binary number A Binary number B Input carry 4-bit sum Output carry 12341234 12341234 12341234 C0C0 C4C4 

12. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed 6. The circuit shown will have identical logic out if all gates are changed to a. AND gates b. OR gates c. NAND gates d. NOR gates © 2008 Pearson Education A B C D

13. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed 7. The two types of gates which are called universal gates are a. AND/OR b. NAND/NOR c. AND/NAND d. OR/NOR © 2008 Pearson Education

14. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed 8. The circuit shown is equivalent to an a. AND gate b. XOR gate c. OR gate d. none of the above © 2008 Pearson Education A B

15. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed 9. The circuit shown is equivalent to a. an AND gate b. an XOR gate c. an OR gate d. none of the above © 2008 Pearson Education A B

16. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed 10. During the first three intervals for the pulsed circuit shown, the output of a. G 1 is LOW and G 2 is LOW b. G 1 is LOW and G 2 is HIGH c. G 1 is HIGH and G 2 is LOW d. G 1 is HIGH and G 2 is HIGH © 2008 Pearson Education A B C D A B C D G1G1 G2G2 G3G3

17. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed 1. For the full-adder shown, assume the input bits are as shown with A = 0, B = 0, C in = 1. The Sum and C out will be a. Sum = 0 C out = 0 b. Sum = 0 C out = 1 c. Sum = 1 C out = 0 d. Sum = 1 C out = 1 © 2008 Pearson Education A B  C out  A B   0 1 0 Sum C out

18. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed 2. The output will be LOW if a. A < B b. A > B c. both a and b are correct d. A = B © 2008 Pearson Education A1B1A1B1 A2B2A2B2 A3B3A3B3 A4B4A4B4 Output

19. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed The next two practical lectures will cover: Introduction to Verilog Gate level modeling with verilog The next theory lecture will cover: 6-4 Comparators 6-5 Decoders 6-6 Encoders