1. Multilevel Partitioning
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2. History The circuit partitioning problem: studied since 1970’s.
The Kernighan-Lin (KL): introduced in 1970.
Extended to Fiduccia-Mattheyses (FM) in 1982.
Little progress: in a period of 15 years
Significant progress: during the mid-to-late-90’s in less than five years
 the best reported cutsize on commonly used benchmarks was reduced by almost 50%.
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4. hMetis Algorithm
“Multilevel Hypergraph Partitioning,” Karypis, Aggarwal, Kumar, Shekhar, DAC 97, pp (Univ of Minnesota)
“Multilevel Circuit Partitioning,” Alpert, Huang, Kahng, DAC 97, pp (UCLA)
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5. Clustering Initial graph Possible clusterings a d a d b c,e b c e d
a,b,c
Initial graph e
Possible clusterings
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6. Multilevel Partitioning Schemes
Produce high-quality partitionings.
Outperformed everything else (for large designs)!
Very fast
Eg: 1M-node graph takes 35s.
Easily parallelized
Eg: 1M-node graph takes 0.8s on 64 processors.
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7. Ingredients of Multilevel Partitioning
Coarsening
Initial Partitioning
Refinement
Successive coarse graphs must make it easier to find a good partition.
Uniform vertex weights.
Exposed edge-weight must decrease rapidly.
The `how to coarsen’ computation must be fast.
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8. Ingredients of Multilevel Partitioning
Coarsening
Initial Partitioning
Refinement
Easiest of the three phases.
Everything reasonable works fine.
e.g. FM.
It requires very little time
Operates on small graphs (~100 vertices).
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9. Ingredients of Multilevel Partitioning
Coarsening
Initial Partitioning
Refinement
Needs a local partitioning refinement algorithm.
Any vertex-swapping algorithm can be used
KL, FM, etc.
If coarsening is done correctly, simple refinement algorithms work extremely well and this phase requires very little time.
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10. Metis: Multilevel Graph Partitioning
Coarsening
Maximal independent set of edges (matching).
Preference to high weight edges: heavy-edge.
Effective in reducing the exposed edge-weight!
Initial Partitioning FM
Refinement
A simplified version of FM
Only up to 4 passes, Early exit
Very fast refinement. 2 1
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11. Coarsening
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12. Coarsening
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13. Number of Levels No. of Levels: logm(|V| / v0) |V|: No. of nodes
v0: No. of nodes in the final (clustered) graph
nodes (can be processed efficiently by FM)
m: cluster ratio
Average number of nodes per cluster (e.g., 3)
1.3 recommended ( how many levels for 1M nodes?)
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14. Going from Graphs to Hypergraphs
Hypergraph partitioning is significantly more complicated than graph partitioning.
Hypergraph Coarsening Schemes:
Edge-based
Hyperedge-based
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15. Hypergraph Coarsening Schemes
Edge-based coarsening schemes
Pairs of connected vertices are collapsed together, using the heavy-edge heuristic.
Easy and fast to compute.
Does not dramatically decrease the exposed hyperedge weight.
Cannot easily remove moderate-size hyperedges.
Requires a lot of refinement in order to obtain good partitionings
Requires sophisticated refinement schemes
Can lead to good partitionings but very slow!
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16. Hypergraph Coarsening Schemes
Hyperedge-based coarsening schemes
Collapses together all the vertices of an entire hyperedge.
Preference is given to the heavier hyperedges.
Easy and fast to compute.
It dramatically decreases the exposed hyperedge weight.
Leads to very good initial partitionings.
3600 as opposed to 6200 for golem3!
Requires very little refinement time.
High-quality partitionings can be obtained with simple refinement schemes.
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17. Coarsening
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18. hMetis: Multilevel Hypergraph Partitioning Algorithm
Uses hyperedge-based coarsening.
Uses a simplified version of FM for refinement
Limits the number of passes, Early-exit
hMetis is an extremely fast, robust, high-quality hypergraph partitioning algorithm.
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19. Cut During One Pass
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20. V-Cycle
Multi-Level Partitioning
V-Cycle
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21. Restricted Coarsening
preserves the initial partitioning that is input to the algorithm.
will collapse vertices together that belong only to one of the two partitions.
Uncoarsening is the same as before.
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22. Multi-Phase Refinement
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23. Bisection Quality
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24. Bisection Runtime
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25. Conclusions
The multilevel paradigm with the right coarsening and refinement scheme works extremely well for hypergraphs.
The quality of the partitionings can be further improved by running the algorithm multiple times.
hMetis: available (binaries for many OS’s) in:
URL:
MLPart: available in source code
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26. Multilevel k-way Hypergraph Partitioning
“Multilevel k-way Hypergraph Partitioning”, Karypis, Kumar, DAC 99.
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27. Why k-way Partitioner?
A k-way partitioning of a hypergraph can be easily computed via recursive bisection.
However, developing an algorithm that directly computes a k-way partitioning has a number of advantages:
Recursive bisection cannot directly optimize global objectives:
SOED (Sum of External Degrees: external degree of e = the number of partitions that is spanned by e
(K-1) -metric as SOED but –1.
A direct k-way partitioning algorithm can better enforce tighter balance constraints.
A direct k-way partitioning can potentially produce better partitionings.
Recursive bisection is by its nature sub-optimal.
A direct k-way partitioning can potentially be faster.
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28. Multilevel k-way Partitioning
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29. Partitioning with Fixed Vertices
FM passively accommodates such fixed constraints.
By not moving fixed vertices.
Caldwell, Kahng and Markov show:
Faster partitioning possible for fixed vertices.
Open question: heuristics that actively exploit fixed vertices.
“Hypergraph Partitioning with Fixed Vertices,” Alpert, Caldwell, Kahng, Markov, TCAD 2000.
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30. Optimality
Optimality, Scalability and Stability Study of Partitioning and Placement Algorithms
Jason Cong, Michail Romesis, Min Xie
ISPD 2003
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31. Optimality
State-of-the-art, multilevel two way partitioning algorithms find solutions very close to the optimal solutions of BEKU benchmarks.
 Existing circuit partitioning techniques are fairly mature
Multiway: 18% worse
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32. FPGA-Based System Partitioning
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33. Multi-FPGA System Motivation: Large systems
FPIC
FPIC
FPIC
FPIC
FPIC: field-programmable interconnect chips
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34. FPGA-Based System
Mapping of a typical system architecture onto multiple FPGAs
FPGA
FPGA
RAM
Logic
Logic
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35. Challenges Multi-way system partitioning onto FPGAs: Key challenges:
Low utilization of FPGA gate capacity
Reason: hard I/O pin limits
Low clock speeds
Reason: long interconnect delays between multiple FPGAs
Long runtimes for system partitioning
Run-time reconfigurability:
 Another dimension added (evolve through time)
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36. Multi-FPGA Partitioning
Primary objective:
No. of FPGAs
Constraints:
Area (FPGA size)
IO (no. of FPGA pins)
Different from single chip partitioning:
Small change in balance and cut size  infeasible partitioning
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37. Multi-FPGA Partitioning
Secondary objective:
After no. of partitions determined, minimize amount of communication
 improve speed
Different from single chip:
Not distinguish the number of FPGAs a net spans to (k)
 minimize k
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38. Summary Circuit netlists can be represented by graphs
Partitioning a graph means assigning nodes to disjoint partitions
The total size of each partition (number/area of nodes) is limited
Objective: minimize the number connections between partitions

39. Summary Basic partitioning algorithms Multilevel partitioning
Move-based, move are organized into passes
KL swaps pairs of nodes from different partitions
FM re-assigns one node at a time
FM is faster, usually more successful
Multilevel partitioning
Clustering
FM partitioning
Refinement (also uses FM partitioning)