1. 13/9/2005N.Manthos, UOI1 Production Testing and Quality Assurance of the CMS Preshower Front-end Chips – PACE3 N. Manthos, University of Ioannina, Greece 11 th Workshop on Electronics for LHC and future Experiments Heidelberg 11-16/9/2005 P. Aspell 1, D. Barney 1, Y. Beaumont 1, W. Bialas1, I. Evangelou 3, A. Go 2, P. Kokkas 3, N. Manthos 3 *, I. Papadopoulos 3, A. Peisert 1, S. Reynaud 1, G. Sidiropoulos 3, A.Tcheremoukhin 4, F. Triantis 3, P. Vichoudis 1,3 1 CERN, Switzerland, 2 NCU, Taiwan, 3 University of Ioannina, Greece, 4 JINR, Russia

2. 13/9/2005N.Manthos, UOI2 Outline Introduction-CMS Preshower PACE3 features PACE3 production run PACE3 test system PACE3 production run evaluation results Summary and conclusions

3. 13/9/2005N.Manthos, UOI3 CMS Preshower Geometry – physical location CMS

4. 13/9/2005N.Manthos, UOI4 CMS Preshower active construction unit-Micromodule PACE3

5. 13/9/2005N.Manthos, UOI5 PACE3C 32-channel switchable-gain pre-amp/shaper with leakage-current compensation, DC coupled to a single silicon sensor (50pF strip capacitance) with multiplexed differential analog readout. In addition includes: an analogue pipeline memory (192 cells), storing data until reception of a level-1 trigger (LV1). FIFO 48 deep (16 LV1s) Internal injection circuit able to explore full dynamic range. Programmable internal DACs for biases/currents etc. measured by connections to external DCU. PACE3C specs: Dynamic range 0.1 - 400 MIPs. Linear response to energy (if possible) Signal to noise ratio of 10 (for calibration using single MIPs). S/N in high gain, HG (with sensor) of >6:1, HG dynamic range 0.1 – 50 MIPs S/N in low gain, LG (with sensor) of ~2:1, LG dynamic range 1-400 MIPs Good memory uniformity. To avoid the need for many pedestals per channel Operate at the LHC bunch crossing frequency of 40 MHz (peaking time ~25ns). LV1 latency 3.2µs programmable. 3 samples per LV1. Possibility to store up to 16 triggers in memory. Skip controller must be able to skip 15x3 consecutive cells etc. Reasonable power consumption. Reliable Programmability through I 2 C. PACE principle specifications - Main Requirements from the CMS Preshower

6. 13/9/2005N.Manthos, UOI6 Assembly of two ASICs Delta3 and PACEAM3 Technology: 0.25um CMOS P.Aspell W.Bialas D.Moraes M.Dupanloup Q.Morrissey Designers: PACE3 unpackaged Engineering run: Early 2005, tested at CERN, Yield ~80%, Yield relatively low due to chips from ALL reticles being packaged – including those at the boundaries of the wafers and some packages with only one chip! Package : 196 fpBGA (15x15 mm) 1mm ball pitch Thickness = 1.7mm PACE3C Delta3 PACEAM3

7. 13/9/2005N.Manthos, UOI7 PACE3 analog chain Internal Calibration Circuit (HP and LP)

8. 13/9/2005N.Manthos, UOI8 50400 0 1.5 3.1 Output Voltage (V) Signal (MIPs) LGHG Calibration of system with real single MIPs. Cal pulse… 1 to 50 MIPs Overlap between the two gains to inter-calibrate. High Precision (HP) Range …. –31.4mV to 31.4mV, lsb = ~0.314mV (Range …. –10 to 10 MIPs, lsb = 1/10 th MIP) Low Precision (LP) Range …. –31.4 mV to 1.256 V, lsb = 7.8 mV (Range …. –10 to 400 MIPs, lsb = 2.5 MIP) Will need to measure LP and HP response periodically to calibrate the calibration circuit. 256 0 ~ 400 MIPs equivalent1.256 Calibration Circuit O/P Voltage Step DAC CalV input value LP HP Match the response of a real MIP with electronic injection pulse 3.14 mV step = 1 MIP Step response from the calibration circuit Overlap between the two gains HP, HG (< 10MIPs) LP, LG (< 400 MIPs) HP, LG (< 10 MIPs) LP, HG (< 50 MIPs) PACE3 Calibration

9. 13/9/2005N.Manthos, UOI9 The Preshower needs 4300 PACE modules Delta PACEAM K The Reticle layout Production run is ~ 48 wafers ~ 150 reticles per wafer Giving : ~14K Delta chips ~21K PACEAM chips MSB LSB UnusedChip Type Reticle X 4 bits Reticle Y 4 bits Wafer No. 6 bits Laser blown 16 bit Chip ID register in Delta, PACEAM read by I 2 C D DP P P K10 00 10 01 11 Note : Delta and PACEAM can be distinguished by reading control register 1 Chip Type coding Production First production phase of packaging: 6 wafers ~ 1840 chips. 63! : rejected due to failure during packaging Package number (laser-printed on the package) 1xxxx, 0xxxx, engineering run wafers 2xxxx, 3xxxx : production run wafers

10. 13/9/2005N.Manthos, UOI10 Tests overview Initial tests Power-on and check current (short circuits?), basic i 2 c communication to chip Digital functionality tests and default values to registers Check all registers (write/read), flip-flops, write default values to registers (Delta, PACEM) Channel (groups of 8 channels) injection tests (LGLP, V 0 cal=200), store the 2 nd sample (check full data path functionality in all channels). Test and calibrate DACs – set optimum values for bias voltages/currents Linearity scan (for dynamic range, gain) Timing scan Optimum sampling point, shape, t p, t r, Calibration procedure. Input from DACs scan - linearity scan to estimate the gain. Skip Controller, memory uniformity and noise in low gain, noise in high gain. Evaluation of the production run chips Standard test procedure Elapsed time ~4min/chip Total operator time ~6 min/chip including the chip insertion/take out from the ZIF socket, etc.

11. 13/9/2005N.Manthos, UOI11 Test system PACE3 testing Hybrid testing PACE3 ZIF socket PACE3 testing daughter board Hybrid testing daughter board PACE3 Test board Based on M16C μController From Agilent E3631A power supply, programmable through RS232 by the PC Pace3 supply lines Programmable delay lines FPGA Altera ACEX ADC: AD41240 12-bit DCU: DCU25F To/from PC (RS232 or USB)

12. 13/9/2005N.Manthos, UOI12 Test system – user interface LabVIEW application

13. 13/9/2005N.Manthos, UOI13 PACE power on current, run current, Power consumption Digital test and default registers Passed chips Average Power on current = 38 mA Average Run current = 209 mA Average Power consumption = (209-38) mA x 2.5 V= 427.5 mW 13 overflow 198 chips were rejected Initial tests Digital tests Digital tests and updating registers 14 chips were rejected

14. 13/9/2005N.Manthos, UOI14 Injection of one event in all 32 channels (internal pulse) Normal response Rejected chip 1 st sample2 nd sample3 nd sample Injection Test failed 14 chips were rejected Channel Injection tests For hybrid tests: Ground bar in all channels. In case of no connection of a channel to bonding pad One channel is not working

15. 13/9/2005N.Manthos, UOI15 DAC spread for optimized values of V 0 Preamp, V 0 Shaper, Spare, VMemRef, VShift, VOutBuf Optimized values for: V 0 Preamp232±2.6 V 0 Shaper90±1.3 VMemRef78±1 VShift151±1.6 VOutBuf158±2 PACE includes 13 8-bit DACs (Vref=2.5V) for bias voltages and currents. They are set to their nominal values and they are measured by the DCU. Example for V 0 Preamp 4 values set to DAC and measured by DCU, Fit. Slope: 3.96mV/DAC div Output of the voltage DACs through a divider to the DCU. Nominal V 0 Preamp=1.8V= 2 (due to the divider)*3.96*DAC value → DAC optimized value=227 Setting PACE nominal biases DAC scan Slope spread of Voltage DACs=0.04 mV/div Slope spread of Current DACs=0.12 mV/div

16. 13/9/2005N.Manthos, UOI16 Gain for LGLP,LGHP, HGLP,HGHP Passed chips Average Gain LGLP= 3.26 ± 0.03 mV/mip Average Gain LGHP= 3.16 ± 0.06 mV/mip Average Gain HGLP= 19.6 ± 0.3 mV/mip Average Gain HGHP= 19.7 ± 0.3 mV/mip 1 underflow 5 chips were rejected Linearity Scan Two gains and two precisions: Pedestal run 2 channels (time consuming proc) injected using full range of V 0 Cal DAC in steps of 2. Pedestal subtracted

17. 13/9/2005N.Manthos, UOI17 Shape of the pulse – rise time t r Using the delay line (IDT Y0207P) in the test system mother board. Find the optimum sampling point, channel to channel variation of the pulse shape Tune the time between ReSynch and Trigger signal. 25 steps of 1 ns Timing Scan trtr 0.9 A 0 0.1 A 0 A 0 tptp

18. 13/9/2005N.Manthos, UOI18 Rise Time (10 to 90%) for high and low gain, Peaking time Analysis to get the analogue parameters of the PACE chips has been performed using only the central time sample. t p spread HG: 0.4 ns Average Rise time HG:15.2 ± 0.4 ns t p spread LG: 0.2 ns Average Rise time LG:13.2 ± 0.4 ns Average t p HG: 25.4 ± 0.4 ns Average t p LG: 23.0 ± 0.3 ns Uncertainty finding the start of the pulse Accepted Range (12-17 ns) No chips were rejected Timing Scan

19. 13/9/2005N.Manthos, UOI19 Dynamic range Calibration- DAC scan Calibration: Conversion of the V 0 Cal to mips for two gains two precisions. One mip has been considered to be 3.5 fC (for a silicon sensor ~320 μm thick) Input: data files from DAC scan DCU ADC conversion factor: 0.465mV/DCU ADC count. Take in to consideration the voltage divider between Delta and DCU: factor= 1.375 for plateau, 1.875 for baseline. mips=0.465(1.375*plateau-1.875*baseline)/3.14 Input: data files from the linearity scans Use of the AD41240 12-bit ADC (Input range 0-2.5V). ADC conversion factor 0.435mV/ADC count. mV=ADC counts *0.435 mV/ADC count Fit a straight line to calculate the average gain Store average gains and mips, mV

20. 13/9/2005N.Manthos, UOI20 Dynamic range Calibration- DAC scan Slope of the fit curves : 1

21. 13/9/2005N.Manthos, UOI21 Dynamic range Calibration- DAC scan Max of the range for LGLP, HGLP where the deviation from the linearity <4% Deviation from linearity= 100*(Injected charge-measured charge)/injected charge LGLP HGLP

22. 13/9/2005N.Manthos, UOI22 trigger 1 trigger 2 trigger 3 trigger 4 Analog memory 192 cells 0 … 191 During the test 15 triggers are applied to block 15x3=45 consecutive cells, and a 16 th one to skip the block of the 45 cells Send multiple triggers and verify that the skip mechanism works Skip mechanism test Final trigger n in the test (5 in the drawing) is arranged so that the skipping mechanism must skip (n-1)x3 cells 5 chips were rejected Skip controller Memory uniformity Noise test trigger 5

23. 13/9/2005N.Manthos, UOI23 DC spread and memory uniformity Low gain Passed chips Mean DC spread = 29 mV Average Memory Uniformity = 0.9 mV 6 chips were rejected 6 overflow 11 overflow Skip controller Memory uniformity Noise test Pedestal rms of each channel through out the memory. 3 events/location Memory uniformity: average of the 32 rms. The rms of the average pedestal values of each channel in all memory cells. For each memory cell 27 events Chan-to-chan DC spread.

24. 13/9/2005N.Manthos, UOI24 Noise of a single cell in the memory for HG, LG Passed chips Average noise HG 1.6 mV S/N=19.6/1.6=12.2 Average noise LG 1.1 mV S/N=3.26/1.1=3.0 No chips were rejected Skip controller Memory uniformity Noise test

25. 13/9/2005N.Manthos, UOI25 #%yield(%) Chips(6 wafers)1840 rejected due to failure during the packaging, 52 of them empty packages! 63 Received1777 Tested1776 Rejected39322.177.9 Power on current out of spec ( 30 - 50 mA ):18910.6 Failed to read Delta/PACE-AM chip ids correctly1508.4 Digital tests failed80.4 Update of PACE-AM registers failed60.3 Run current out of spec (150 - 250 mA)70.4 Current consumption out of spec (150 - 200 mA) 20.1 Injection test failed (all channels)140.8 Gain in LGHP out of spec (2.8 - 3.4).20.1 Gain in HGLP out of spec (18.5 – 22)10.1 Gain in HGHP out of spec (18.5 - 22)20.1 Memory uniformity out of spec (0 – 2 mV)10.1 Channel-to channel DC levels out of spec(0-50mV)50.3 Skip controller test failed50.3 At least one channel has zero noise10.1 Test results – Yield The Yield could be increased to >95% If the 1st two reasons of failure can be resolved

26. 13/9/2005N.Manthos, UOI26 Test results – Yield –map of the package-tested chips vs package number There are groups of rejected chips with adjacent package number. PACE production evaluation summary Passed production evaluation Failed production evaluation Failed during packaging. ~90% of them empty packages Not tested

27. 13/9/2005N.Manthos, UOI27 Test results – Yield –packaged-tested chips vs their location in the wafer Although the packaging company got the instruction to use chips (Delta and PACEAM) from the reticles with number 1 and 0, they have used chips near to the border of the wafer where we knew from the engineering run that they will have problems Dark: PACEAM not used for the production run (chip id=1) White: Delta and PACEAM used (packaged) for the production run Delta PACEAM K The Reticle layout

28. 13/9/2005N.Manthos, UOI28 Summary and Conclusion 1776 packaged PACE3 chips from the production run were extensively tested. 1776 packaged PACE3 chips from the production run were extensively tested. The test system developed for the production evaluation performs fine. The test system developed for the production evaluation performs fine. ~ 6 min are needed for the test of each chip. Very small spread of gain, of pulse shape and noise observed between the chips. Very small spread of gain, of pulse shape and noise observed between the chips. Their dynamic ranges follow the specifications. Their dynamic ranges follow the specifications. The production Yield is ~78%. The production Yield is ~78%. More study is needed to understand why the rejected chips are not passing those More study is needed to understand why the rejected chips are not passing those tests which reducing the yield significantly. tests which reducing the yield significantly. The test data have been stored in the CRISTAL database. The test data have been stored in the CRISTAL database. Similar tests will be performed in the hybrid and micro-module level Similar tests will be performed in the hybrid and micro-module level using the same main hardware and software. using the same main hardware and software. 38 more production run wafers (~38 x 300 PACE3 chips) exist. 38 more production run wafers (~38 x 300 PACE3 chips) exist. Chips taken from more central area of the wafer from 20 wafers will be packaged at Chips taken from more central area of the wafer from 20 wafers will be packaged at the end of September. the end of September. They will be tested at Ioannina this autumn. They will be tested at Ioannina this autumn.