1. ATLAS Strip Tracker Stavelets or A Tale of Two Stavelets “It was the best of times, it was the worst of times, it was the age of wisdom, it was the age of foolishness, it was the epoch of belief, it was the epoch of incredulity, it was the season of Light, it was the season of Darkness, it was the spring of hope, it was the winter of despair...” Charles Dickens, “A Tale of Two Cities” Peter W Phillips STFC Rutherford Appleton Laboratory On behalf of The ATLAS Strip Tracker Stavelet Community TWEPP, Vienna, September 26-30 2011

2. ATLAS Phase II Tracker Upgrade Challenges facing HL-LHC silicon detector upgrades Higher Occupancies ⤷ Finer Segmentation Higher Particle Fluences ⤷ Increased Radiation Tolerance Larger Area (~200 m 2 ) ⤷ Cheaper Sensors More Channels ⤷ Efficient power distribution ⤷ Maintain control over cable counts! Phase 2 (HL-LHC, previously sLHC) Replacement of the present Transition Radiation Tracker (TRT) and Silicon Tracker (SCT) with an all-silicon strip tracker Conceptual Tracker Layout Short Strip (2.4 cm)  -strips (stereo layers): Long Strip (4.8 cm)  -strips (stereo layers): r = 38, 50, 62 cm r = 74, 100 cm Record events Like these...... with the minimum number of these 2

3. The Stave Concept ~ 1.2 meters Bus cable Hybrids Coolant tube structure Carbon honeycomb or foam Carbon fibre facing Stave Cross-section Alternate Solution: The Supermodule Demonstrator with 8 double sided modules and DC-DC converters being assembled and evaluated at CERN. Latest results encouraging – but this is not the subject of my talk! A Stavelet is a shortened stave prototype with up to four modules on each side. Results will be reported here for: A Serially Powered Stavelet with four modules A Stavelet with two modules and DC-DC converters Designed to reduce radiation length  Minimize material by shortening cooling path  Modules glued directly to a stave core with embedded pipes Designed for mass production  Simplified build procedure  Minimize specialist components  Minimize cost Stavelets 3

4. Stavelet Bus Tape Layout Shield Layer (Al) SP Trace Layer (Cu) LVDS Clock/Command/Data & NTC SP Current Return HV 4 For DC-DC, the power section of the SP tape is cut off and replaced by a custom section 100  m track/gap over 40cm (1.2m)

5. The Short Strip Stave Module One Sensor – n-in-p, 10cm * 10cm approx – 4 columns of ~2.5cm strips – Single backplane connection in design Two Kapton Hybrids – Glued directly to sensor for minimal mass Each Hybrid has – 20 ABCN-25 ASICs arranged in 2 columns – Integrated SP shunt control circuitry ABCN-25 ASIC – Binary architecture: 128 channels of trimmable preamplifier/discriminator, pipeline and control logic – LDO to produce 2.2V analogue power from 2.5V digital – Dual (redundant) shunt transistors Expected Operating Threshold – 0.7fC 5

6. Other parts of the Stavelet System Custom Current Source – 0-6A, 80V – Over Voltage protection Power Protection Board (PPB) – Slow Control bypass (one wire) – Over Voltage protection – Socket for alternate SP shunt circuits Such as pictured M shunt plugin – Also gives access to hybrid power and ground Handy for testing novel SP chains or adding passives BCC board – Basic Control Chip and passives – Handles AC coupled LVDS reception, generation of 80 MHz DCLK and multiplexing of the two column data streams into one 160Mbit output M-shunt plugin Power Protection Board BCC Board 6 Custom Current Source

7. Stave Module Tests ParallelSerialDC-DC Hybrid 62590 e - 596 e - 590 e - 599 e - 595 e - 603 e - Hybrid 61585 e - 591 e - 588 e - 599 e - 585 e - 591 e - 598e DC-DC converters Individual stave modules have been tested with three basic powering configurations Parallel powering, serial powering, DC-DC Use frame PCB + BCC boards (not PPB) All give results in line with expectation However note the aluminium cooling block AC or DC coupled to each hybrid GND plane through Beryllium Copper springs Provides a low impedance route for signals passing between the hybrids Hybrid 61 Hybrid 62 Serial Power Chain AC Coupled Clock/Command Input noise: 588e - Input noise: 599e - Input noise: 590e - Input noise: 599e - Serial Powering Column 0 Column 1 Column 2 Column 3 Column 0 Column 1 Column 2 Column 3 7

8. Serially Powered Stavelet

9. Chain of Hybrids, individual shield pads H0H1H2H3H4H5H6H7 Column0123456789101112131415 DC AC DC AC DC AC DC ENC671622632678646624621652657633627651670651619649 As first built, the current is routed between a module’s two PPB boards by means of wirebonds and the bus tape, and the distributed shunt transistors are controlled by circuitry built into the hybrid. Separation of the sensor shield pads, with each hybrid either DC or AC coupled to its sensor’s shield, brought down the noise in comparison to the (common shield) results shown at TWEPP last year. That looks OK: where’s the catch? V I 0V 2.5V5V 7.5V10V12.5V15V17.5V20V 9

10. The three point gain test used for ENC measurements uses optimistic trigger conditions – Cal pulse / trigger / readout / delay – Never more than one event in the pipeline In physics we would have random triggers, with many in the pipeline at once – Design a test to look for potential issues Send two triggers separated by a controlled, but variable number of clocks – Repeat for a series of fixed thresholds – Look for changes in occupancy – Look for voltage or current bumps correlated with the readout cycle With the ABCN25 chip, command reception triggers a surge in current – dV occurs between the power rails – This may inject signals into the front end Looking for signals correlated with readout: The Double Trigger Noise Test Note: Scope is in AVERAGING MODE Custom Current Source @ 5A, HV 230V, Two L1A separated by 134 BCO, dV => diff probe between hybrid 0V & 2V5 Trigger DATA dV 150nS = 6 *40MHz clock period 10

11. DTN Plots and a Very Basic Metric 11 Stavelet M0 (H0/H1) DTN at 0.5fC Sum(hits): simply sum the number of hits shown in each double trigger plot 592687 622771 95 82 Time (n clock periods) Channel H0 H1 6 clock periods =150nS

12. Initial SP Stavelet DTN results H0H1H2H3H4H5H6H7 Column0123456789101112131415 ENC671622632678646624621652657633627651670651619649 DTN @ 1.0fC 1876462710010874822252003671537543801381612858200 DTN @ 0.75fC 20881325294710415786546794554493706284518921125224494129421704 DTN @ 0.5fC 5926876227719582667370798654762021159136050866820983092155795611656778574268711845 Sum(hits) Column Number 12 At certain points of the readout cycle, even at 1fC threshold, every second hybrid had unacceptable high occupancy 

13. DTN Results for a Single, Serially Powered Stavelet Module Double trigger noise results were initially disappointing. Lots of options tested, including: Adding capacitors across each hybrid Using external control of ABCN-25 shunts Two combinations found useful: Use of external shunt control with capacitors across the module SP input (shown here) still “Chain of Hybrids” at 5A CI Setting both hybrids to the same DC potential now “Chain of Modules” at 10A CI How may this transfer to the stavelet? BEFOREAFTER 1.0fC 0.5fC 0.75fC Double Trigger Noise now clean at 0.75fC (apart from the known bad chip) 20 0 0 0 76 0 0 0 576 667 145 190 244059 272463 193 120 3757 6431 88 124 135 136 0 0 Capacitors 13

14. Coupled M-shunt Plugins Wirebonds pulled to break original route. SP current path between hybrids is now PPB -> plugin -> BRAID -> plugin -> PPB Each plugin has 10uF added between SP in/out. 14 611 693 64 238 BEFORE: DTN @ 0.5fC AFTER: DTN @ 0.5fC 611656 778574 2687 11845 H6 H7 H6 H7

15. Chain of Hybrids with Coupled M-shunt Plugins 0V 2.5V 5V7.5V10V H0H1H2H3H4H5H6H7 Column0123456789101112131415 ENC667627634682667649689750673646644680 663640673 DTN @ 1.0fC 0000000000000000 DTN @ 0.75fC 0000000000000000 DTN @ 0.5fC 108558266242932979586298359287655456529158 The bonds routing current between a module’s two PPB boards have been pulled. Instead, the circuit is completed by copper braid. Disconnection of the original route is of critical importance wrt DTN results. 12.5V 22.3 Compared to original result, DTN now clean at 0.75fC but ENC is UP  15

16. Chain of Modules 0V 2.5V 5V7.5V10V H0H1H2H3H4H5H6H7 Column0123456789101112131415 ENC661623628675650636697760687646640666680661624656 DTN @ 1.0fC 0000000000000000 DTN @ 0.75fC 0000000000000000 DTN @ 0.5fC 1304015831255118132456102502650237 In this configuration, implemented by means of hookup wire, both hybrids of a module are at the same DC potential with respect to ground. This provides a DC route for return currents passing between the hybrids. 16 Compared to original result, DTN now clean at 0.75fC but ENC is UP 

17. SP Stavelet Summary A serially powered stavelet fitted with four single sided short strip silicon detector modules has been constructed. – System functionality successfully demonstrated: bypass system, custom current source – Initial ENC results close to expectation Detailed investigation reveals susceptibility to noise signals correlated with readout activity – Reduced to acceptable levels by lowering the impedance of the SP chain within a module – In future, suggested to replace PPB by a single unit covering one complete module Have also learnt much about signal paths within the module from the DC-DC stavelet programme, as you are about to see – Discussion started to define a revised SP bus tape design Lower impedance “shield” connections, and more of them Lower impedance backplane connections, and more of them – Design of Serial Power & Protection (SPP) Chip near completion Will add pass transistor to allow either hybrid to be turned off as part of a “STAR” configuration Work will continue to determine the best balance of performance 17

18. DC-DC Stavelet

19. STV-10 DC-DC Converter Single module tests gave encouraging results – Close agreement with reference values More difficult to get good results on the stavelet – Without the low impedance reference plane provided by the single module’s aluminium cooling block, one needs to consider current paths carefully to get good results Peak power requirement of one 20 chip ABCN-25 hybrid – 5 A at 2.5V – Exceeds capability of AMIS series rated for 130nm designs Dedicated DC-DC module provided by the CERN group based on commercial chip – LT3605 Made in two variants – SM01C connectorised For supermodule program – STV10 (pictured) wire-bondable For stave programme Stave module has two ABCN-25 hybrids with a common silicon sensor – One STV-10 converter per hybrid 19

20. (1) Both converters powered from the bus (2) Each converter powered from its own PSU DC-DC Stavelet Module (1) With both converters powered from the bus (1), the “upper” hybrid has ~120 ENC excess noise. Running each converter from a separate power feed (2) halves this excess to ~60 ENC. In configuration (1) the power bus return trace provides a route between the two hybrid ground planes which runs parallel with the shield. Power currents flow through this trace (and hence the shield): increased noise is the result. In configuration (2), separation of the power feeds has removed this possibility. 20

21. (3) ”STAR” configuration with Single backplane connection DC-DC Stavelet Module (2) Moving to the “STAR” configuration (3) yields results similar to the original one, however it should keep currents related to other modules out of the local loop. Adding a second backplane connection (4) makes all the difference. Each hybrid now has its own HV bypass capacitor: the return path for signals originating in the “upper” hybrid need no longer involve the bypass cap of the “lower” hybrid. Both hybrids now have the same ~40 ENC excess noise. Proceed to mount a second module in configuration (4)! (4) “STAR” configuration with Dual backplane connections 21

22. DC-DC Stavelet with Two Modules H0 H1 H2 H3 No significant deterioration in performance of H0/H1 Previously 45 / 42 ENC extra with 140  m copper shield Second module better than the first, perhaps because hookup implemented more neatly “STAR” formed using thicker wire 4 bonds (not 2/3) at each shield connection Second backplane connection wire is shorter Extra Noise compared to Reference Data ShieldH0H1H2H3 100  m Cu 62601126 140  m Cu 5846824 ENC 22 PRELIMINARY

23. DC-DC Stavelet ENC Comparison Single Module Reference Data (composite) 80 MHZ dclk DC-DC Stavelet Result 40 MHz DCLK, 140 um Cu Shield 23 PRELIMINARY

24. DC-DC Stavelet DTN Performance H0 H1 H2 H3 181 38 119 324 1 1 3 31 Double Trigger Noise @ 0.5fC, 140  m copper shield Double Trigger Noise test shows no excess occupancy at 1.0fC or 0.75fC thresholds: the plots are completely clean. Occupancy at 0.5fC is acceptable for both  m and 140  m copper shields. 24 PRELIMINARY

25. DC-DC Stavelet Summary A DC-DC stavelet fitted with two single sided short strip silicon detector modules has been constructed. The first of its modules went through many different hookup configurations before reasonable performance was achieved – Important that each module is connected to the stavelet power bus at only one point to avoid dVs related to currents of other modules – The “shield” in fact becomes a reference plane to which each hybrid ground plane must be well connected in order to optimise signal returns from the common detector. – We also need two backplane connections! The 100 micron copper shield over the DC-DC toroid is more than sufficient – Very little difference moving to 140 micron copper shield – Will proceed to evaluate thinner shield coatings We shall proceed to add the remaining modules to the stavelet – And to tidy up the hookup of the original module, as far as possible Discussion started to define a revised DC-DC bus tape design – Lower impedance “shield” connections, and more of them – Lower impedance backplane connections, and more of them – Implement “STAR” point as part of the bus tape and/or PCB 25

26. Overall Summary Serially powered and DC-DC stavelets have been constructed to study system issues of the ATLAS short strip tracker – Similar ENC values for both schemes – Slightly better DTN performance for DC-DC, but both acceptable – Our evaluation and optimisation continue To date, either technology would be a viable powering solution for the ATLAS short strip tracker – No showstoppers! Have learnt a lot about the details of stave module hookup – Illustration of the importance of realistic system studies! – Plan to revise designs to allow a cleaner implementation 26

27. BACKUP

28. 28 programmable current source has been prototyped (J.Stastny, ASCR) specifically designed for stave09 (ABCN-25), output up to 80V at 6A current setting resolution 2mA isolated USB interface overvoltage protection it should work well also for ABCN-13 now under test with stavelets at RAL Programmable Constant Current source

29. Shield Connections Shield Connections Original Backplane Connection Shield Referencing 29

30. Hybrid 0 Hybrid 1 Hybrid 2 Hybrid 3 Hybrid 4 Hybrid 5 Hybrid 6 Hybrid 7 Initial SP Stavelet DTN result: DTN at ~1.0fC 30

31. Chain of Modules with Two Backplane Connections 0V 2.5V 5V7.5V10V H0H1H2H3H4H5H6H7 Column0123456789101112131415 ENC654619632678649636671722695650645669691668620647 DTN @ 1.0fC 0000000000000000 DTN @ 0.75fC 0000000200000000 DTN @ 0.5fC 401210622598160713319421216660265 In this configuration, implemented by means of hookup wire, both hybrids of a module are at the same DC potential with respect to ground. This provides a DC route for return currents passing between the hybrids. 31 Compared to original result, DTN now clean at 0.75fC but ENC is UP 

32. Chain of Hybrids + Braid + Two Backplane Connections 0V 2.5V5V7.5V10V H0H1H2H3H4H5H6H7 Column0123456789101112131415 ENC659620634684655634N/A 649618645673693667633663 DTN @ 1.0fC 000000N/A 00000000 DTN @ 0.75fC 0000414N/A 00000000 DTN @ 0.5fC 1133618532513N/A 2171435947747252 This test was made after the “chain of modules” trial. Unfortunately the PPB board serving H3 had moved, breaking critical bonds such that the bypass was active. Hence H3 could not be operated in this test. 20.3 12.5V15V17.5V7.5V 32 Compared to original result, DTN now clean at 0.75fC but ENC is UP 

33. DC-DC Stavelet ENC Comparison (2) 40 MHz DCLK, 100um copper shield40 MHz DCLK, 140um copper shield 33 PRELIMINARY