1. Nano and Giga Challenges in Microelectronics Symposium and Summer School Research and Development Opportunities Cracow Sep. 13-17, 2004 Afternoon 4: Carbonanotubes and Molecular Electronics (3:00pm-6:15pm), Mon., Sep. 13 th, 2004 Electrostatic Characteristics of Carbon Nanotube Array Field Effect Transistors Yiming Li, Jam-Wem Lee, and Hong Mu chou Department of Computational Nanoelectronics, National Nano Device Laboratories Microelectronics & Information Systems Research Center, National Chaio Tung University Department of Electrophysics, National Chaio Tung University 1001 Ta-Hsueh Rd., Hsinchu 300, Taiwan

2. Introduction  Carbon nanotube (CNT) field effect transistors (FETs) with promising nanoscale device characteristics have recently been explored  For ultrasmall nanoscale FETs, CNT FETs have provided fascinating characteristics by comparing with silicon-based metal-oxide-semiconductor FETs (MOSFETs)  For CNT FETs with a planar bottom gate electrode configuration, the CNT is un-passivated  The larger thickness of the back gate dielectric and the lower dielectric constant of the air surrounding the CNT result in a small gate-to-nanotube capacitance and produce the lower on- state current

3. Introduction  For the top gate geometry, the CNT is covered by a gate insulator and demonstrates several advantages over the case of bottom gate, such as lower operating voltage due to stronger coupling between the gate and the nanotube, and more flexibility to control individual devices  For CNT FETs with a wrap around gate, the CNT is surrounded by a cylindrical gate and this coaxial structure exhibits the strongest capacitive coupling between the gate and the tube  Among these three structures, it is known that single CNT can only contribute little driving current, array of CNT has been considered as a candidate to improve the electrical characteristics and physical properties (e.g., driving capability) of CNT FETs

4. Introduction  For a CNT array, the screening of the charge induced by CNTs significantly affects the structure’s electrostatic characteristics, such as capacitance, in particular when many CNTs are in close proximity  A unified investigation on the electrostatic characteristics with a multidimensional electrostatic simulation will clarifies the main difference among various CNT FET arrays and benefits the design and fabrication of CNT FET devices  We in this paper study the electrostatic characteristics and the gate capacitance for a carbon nanotube (CNT) array with three structures of gate electrode: (1) top gate, (2) wrap around gate, (3) and bottom gate CNT field effect transistor (FETs).

5. Introduction  Taking the structure’s radius and gate length of CNT FET into consideration, the three-dimensional (3D) electrostatic simulation and corresponding gate capacitance are calculated and compared using adaptive finite volume method  It is found that there is 20% difference in calculating gate capacitance between 2D and 3D modeling and simulation  3D simulation shows that a wrap around gate gives the largest gate capacitance among structures  A bottom gate possesses the weakest gate controllability  Results of the 3D electrostatic simulations can also be applied to estimate the magnitude of on-current of CNT FETs.

6. Computational Device Structures Illustration of the three simulated (a) bottom, (b) top, (c) and wrap around gate structures in the array of the CNT FET (a) bottom (b) top (c) wrap around gate structures

7. Computational Device Structures  A 3D Laplace equation is solved for the studied CNT FETs structures  The finite volume method is used to discretized the simulation domain  The adaptive computing technique is applied to perform the error estimation and mesh refinement  A preconditioned conjugate gradient method is developed to solve the system of algebraic equations

8. Results and Discussion (a) bottom (b) top (c) wrap around gate structures The simulated potential for the (a) bottom, (b) top, (c) and wrap around gate structures

9. Results and Discussion The gate-to-end-tub (dash line) and gate-to-middle-tube (solid line) capacitances versus the pitch distance

10. Results and Discussion The 3D/2D capacitance ratio vs. pitch distance. The dash and solid lines are the gate-to-end-tub and gate-to-middle-tub capacitance ratios, respectively

11. Results and Discussion The gate-to-middle-tube capacitance vs. pitch distance simulated for the wrap around structure with its gate length from 5nm to 20nm. The right figure shows that the gate-to-end-tube capacitance vs. pitch distance

12. Results and Discussion The gate-to-middle-tube capacitance vs. pitch distance simulated for the top gate structure with its gate length from 5nm to 20nm. The right figure is the gate-to-end-tube capacitance vs. pitch distance

13. Results and Discussion The gate-to-middle-tube capacitance vs. pitch distance simulated for the bottom gate structure with its gate length from 5nm to 20nm. The right figure is the gate-to-end-tube capacitance vs. pitch distance

14. Results and Discussion The extracted fringing capacitance vs. pitch simulated for both the top gate and wrap around gate structures

15. Conclusions We have studied the gate capacitance for a CNT array with three different gate electrode structures: (1) top gate, (2) wrap around gate, (3) and bottom gate CNT structures Taking the structure’s radius and gate length of CNT FET into consideration, the three-dimensional potential distribution and corresponding gate capacitance have been calculated using adaptive finite volume method It has been found that there is 20% difference in calculating capacitance between 2D and 3D modeling and simulation Results of the 3D electrostatic simulations can also be applied to estimate the magnitude of on-current of CNT FETs.

16. Thank you for your attentions!