1. Mork Family Department of Chemical Engineering and Materials Science Si JFET-Controlled Carbon Nanotube Field Emitter Arrays Qiong Shui 1, Martin Gundersen 1,2, Ryan J. Umstattd 3, Chongwu Zhou 2, Alan M. Cassel 4, lJonathan Shaw 5, and David S. Y. Hsu 5 1 Department of Chemical Engineering and Materials Science,University of Southern California, Los Angeles, CA, 90089-0271 2 Department of Electrical Engineering – Electrophysics,University of Southern California, Los Angeles, CA, 90089-0271 3 Physics Department, Naval Postgraduate School, Monterey, CA, 93943 4 Center for Nanotechnology, NASA Ames Research Center, Moffett Field, CA, 94035 5 Naval Research Laboratory, Washington, DC, 20375 IntroductionIntroduction Fabrication Process MeasurementsMeasurements Simulation Results for Si JFETs Future Work 1. C. A. Spindt, "A thin-film field-emission cathode," J. Appl. Phys., vol. 39, pp. 3504-3505, 1968. 2. T. Utsumi, "Keynote address vacuum microelectronics: What's new and exciting," IEEE Transaction on Electron Devices, vol. 38, pp. 2276-2283, 1991. 3. http://other.nrl.navy.mil/CREBWorkShop/Jensen.pdf CNTs Field Emitter Applications 1. Providing the electron beam(s) inside of flat panel field emission displays(FED) [3] lower power consumption Wider view angles Viewable from any angle with no change in brightness, contrast or color Faster response time 2. Providing the electron beam in vacuum microwave amplifiers/oscillators 3. Providing the electron beam for charge neutralization when using ion thrusters for propulsion in space Motivation 1. The introduction of Spindt microtip [1] cold cathodes has led to great interest in the pursuit of electron beam sources for flat panel display and vacuum microelectronic devices 2. CNTs are the closest one that have “ideal” field emitters [2] Stable at high temperature Have high electrical and thermal conductivity Exhibit ballistic electron transport. 3. Stability and lifetime are two important issues to be addressed before field emitters find wide applications Active devices, JFETs, were proposed in our study to control the stability of the emission current of CNTs ReferencesReferences The left figure (Fig. 1) shows Si post JFET structure for simulation of breakdown voltages of JFETs. The right figure (Fig. 2) shows the breakdown voltage of the JFETs when ion implantation energy are at 150 keV and 200 keV, respectively Fig. 3 Boron impurity distribution in Si simulated by SRIM-2003 at an ion implantation energy of 150keV and a dose of 5  10 15 /cm 3. Fig. 4 Drain Voltage vs. Id for the built-in JFET at different V gs. (a). Deposit Cr/Au (b). Etch Si post by Electron Cyclotron Resonance etcher (e). Deposit SiO 2 by PECVD and Cr to pattern the extraction gate (g). Etch Cr and SiO 2 to open windows for emitter sites (i). Grow CNTs by PECVD at 700 ° C (h). Deposit the buffer layer Cr (40nm) and the catalyst layer Ni (20nm) for CNTs growth (f). Define the control gate (c). Boron was ion implanted to form P+ regions The Pulsed Power Group of USC thanks the Air Force Office of Scientific Research for their generous support. AcknowledgementAcknowledgement P+ Cr SiO 2 N- Si substrate N+ Extraction Gate Control Gate Fig. 5 Leakage current vs. the voltage between the extraction gate and the control gate. The thickness of SiO 2 is 1  m. the calculated resistivity of our deposited SiO 2 at 25 °C is about 6  10 12 Ω-cm. Fig. 7 SEM images(left and right) of vertically aligned CNTs grown on Si post JFETs. The tilt angle for taking the images is 85 °. Fig. 6 SEM image shows the structure after Cr and SiO 2 were etched through the patterned 2  m diameter emitter sites Test the emission current of CNT emitter arrays and its stability Optimize the fabrication process