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Tools - Analyzing your results - Chapter 7 slide 1 Version 1.5 FPGA Tools Course Analyzing your Results.

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Presentation on theme: "Tools - Analyzing your results - Chapter 7 slide 1 Version 1.5 FPGA Tools Course Analyzing your Results."— Presentation transcript:

1 Tools - Analyzing your results - Chapter 7 slide 1 Version 1.5 FPGA Tools Course Analyzing your Results

2 Tools - Analyzing your results - Chapter 7 slide 2 Version 1.5 In this chapter, you will learn How to check the status of your design Key information contained in each file How to verify timing specifications How to verify design performance

3 Tools - Analyzing your results - Chapter 7 slide 3 Version 1.5 Outline Design Manager and Report Browser Report Files –Translate –Map –Logic Level Timing –Place and Route –Post Layout Timing –Pad report –Asynchronous Delay –Bitgen Summary Quiz

4 Tools - Analyzing your results - Chapter 7 slide 4 Version 1.5 The Flow Log File The Flow log file, fe.log, displays –Commands –Screen display –Implementation status –All errors and warning message To view the Flow Log File: –Alliance users: select Utilities -> Flow Log file –Foundation users: from the Project Manager Window, select Reports -> Implementation Log File Fe.log file

5 Tools - Analyzing your results - Chapter 7 slide 5 Version 1.5 Implementation Design Flow NGDBUILD Merge Hierarchical Design MAP Logical to Physical translation Groups LUTs and FFs Into CLBs TRCE Static Timing Analysis BITGEN Generates configuration file TRCE Static Timing Estimates PAR Layout of Physical Design Routes Physical Design UCF User Constraint File Configuration Program the FPGA or CPLD XNF or EDIF netlist

6 Tools - Analyzing your results - Chapter 7 slide 6 Version 1.5 The Report Browser Reports are shown when available –Double-click to open –Yellow sparkles indicates new (not yet read) Displays all commands executed by Design Manager and design status From Design Manager, select Report Browser From Foundation Project Manager, Select Reports -> Implementation Report Files

7 Tools - Analyzing your results - Chapter 7 slide 7 Version 1.5 Report Files Report files are generated throughout implementation: –DRC checks are reported in many of these files

8 Tools - Analyzing your results - Chapter 7 slide 8 Version 1.5 Outline Design Manager and Report Browser Report Files –Translate –Map –Logic Level Timing –Place and Route –Post Layout Timing –Pad report –Asynchronous Delay –Bitgen Summary Quiz

9 Tools - Analyzing your results - Chapter 7 slide 9 Version 1.5 Translate Report Lists translate command and source files used in implementation Lists any missing blocks in the design Lists nets with no source or no driver File name is design_name.bld ngdbuild: version M1.4.12 Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc4000e -u -uc C:\labs\nrpipe\Pipe.ucf C:\labs\nrpipe\Pipe.xnf xc4000e.ngd Launcher: Using rule XNF_RULE Launcher: Pipe.ngo being compiled because it does not exist Launcher: Running xnf2ngd from C:\labs\nrpipe\xproj\ver1\ Excerpt of Translate Report

10 Tools - Analyzing your results - Chapter 7 slide 10 Version 1.5 Map Report Determine if your design fits in the selected FPGA –Lists FPGA resources used by your design Check for DRC errors and suggestions File name is map.mrp Design Summary -------------- Number of errors: 0 Number of warnings: 14 Number of CLBs: 32 out of 196 16% CLB Flip Flops: 64 4 input LUTs: 32 3 input LUTs: 16 (16 used as route-throughs) Number of bonded IOBs: 24 out of 112 21% IOB Flops: 0 IOB Latches: 16 Number of global buffers: 3 out of 8 37% Excerpt of map.rpt

11 Tools - Analyzing your results - Chapter 7 slide 11 Version 1.5 Logic Level (Pre-Layout) Timing Report Based on block delays and minimal estimated net delays Analyze timing constraints before Place and Route for fast designs –Minimize lengthy implementations File name is map.twr

12 Tools - Analyzing your results - Chapter 7 slide 12 Version 1.5 Timing Report Example (1) Small circuit with AND gate driving register is constrained with 3 ns period Which components and nets are affected are constrained? A1 IPAD OPAD IBUF BUFG AND2 FDCE OBUF D Q CLK A1_IN A1BUF A2 AND1 FF1 CLK_PAD CLK_P CLK

13 Tools - Analyzing your results - Chapter 7 slide 13 Version 1.5 Timing Report Example (2) Resulting Logic Level Timing Report What is the minimum period? Was there a timing error? ======================================================================= Timing constraint: TS01 = PERIOD TIMEGRP "CLK1" 3 nS HIGH 50.000 % ; 2 items analyzed, 0 timing errors detected. Minimum period is 2.918ns. ----------------------------------------------------------------------- Slack: 0.082ns path A1IN to OREG relative to 3.000ns delay constraint Path A1IN to OREG contains 2 levels of logic: Path starting from Comp: IOB.PAD To Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------- -------- IOB.I1 Tpid 1.089R A1IN A1 A1BUF CLB.F2 net (fanout=1) e 0.959R A2 CLB.K Tick 0.870R OREG AND1 FF1 ----------------------------------------------------------------------- Total (1.959ns logic, 0.959ns route) 2.918ns (to CLK) (67.1% logic, 32.9% route) Summary Total delay Delay though IOB Estimated net delay Setup delay

14 Tools - Analyzing your results - Chapter 7 slide 14 Version 1.5 Timing Report Example (Detail) (3) Path starting from Comp: IOB.PAD To Delay type Delay(ns) Phys/Log Res. ----------------------------------------------------------- ------------- --------------- IOB.I1 Tpid 1.089R A1IN A1 A1BUF CLB.F2 net (fanout=1) e 0.959R A2 CLB.K Tick 0.870R OREG AND1 FF1 --------------------------------------------------------------------------------------------- Total (1.959ns logic, 0.959ns route) 2.918ns (to CLK) (67.1% logic, 32.9% route) Delay though IOB Estimated net delay OPAD D Q CLK FF1 CLK_PAD CLK_P CLK AND1 A1 A1_IN A1BUF A2 Setup Delay though AND1 and Setup delay

15 Tools - Analyzing your results - Chapter 7 slide 15 Version 1.5 PAR Report Created after Map, called design_name.par Displays status of layout and constraints –Timing score: zero if design met timing all constraints. *Number of paths missing time constraint and amount of time missed per constraint determine timing score Timing Score: 452 WARNING:baspw:101 - Timing constraints have not been met. Asterisk(*)preceding a constraint indicates it was not met. ----------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels ----------------------------------------------------------- * TS01 = PERIOD TIMEGRP | 3.000ns | 3.304ns | 2 "CLK1" 3 nS HIGH 50.0 % | | | ----------------------------------------------------------- 1 constraint not met. Writing design to file "andff.ncd". All signals are completely routed.

16 Tools - Analyzing your results - Chapter 7 slide 16 Version 1.5 Pad Report Lists cross reference of pads and package pins File name is design_name.pad Design_name.pad

17 Tools - Analyzing your results - Chapter 7 slide 17 Version 1.5 Post-Layout Timing Report Same data as Pre-Layout Timing report, EXCEPT delays are based on routing Use to verify that your design met timing specifications File name design_name.twr Post layout timing report

18 Tools - Analyzing your results - Chapter 7 slide 18 Version 1.5 Asynchronous Delay Report Lists delay of 20 nets with longest delay Lists each net in the design with delay File name is design_name.dly...

19 Tools - Analyzing your results - Chapter 7 slide 19 Version 1.5 Bitgen Report Called design_name.bgn Created after configuration file is created by Bitgen Lists any errors found by Bitgen

20 Tools - Analyzing your results - Chapter 7 slide 20 Version 1.5 Outline Design Manager and Report Browser Report Files –Translate –Map –Logic Level Timing –Place and Route –Post Layout Timing –Pad report –Asynchronous Delay –Bitgen Summary Quiz

21 Tools - Analyzing your results - Chapter 7 slide 21 Version 1.5 Questions What are the main functions of the Translate and Map programs? What is the difference between the Logic Level Timing Report and the Post-Layout Timing Report? What information is found in each file? Which file would you use to find the following: –Percent of the FPGA used by your design? –Did your design completely route? –Did your design meet constraints?

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