1. 4 November 2002Paul Dauncey - Electronics1 UK Electronics Status Paul Dauncey Imperial College London

2. 4 November 2002Paul Dauncey - Electronics2 Back end electronics for ECAL 30 layers, 18  18 pads/layer, total 9720 channels Each channel amplified at front end by VFE chip CR-RC shaper, peaking time ~180ns 18 channels/VFE chip, multiplexed analogue output Need to generate sample-and-hold at peak time Need to drive multiplex shift register Need to digitise with 14 bits range, 10 bits precision Need to send calibration voltage for pulse injection Need to run at ~100Hz sustained, ~1kHz peak rate Read out all channels every event for pedestal and noise studies For more details, see: http://www.hep.ph.ic.ac.uk/calice/electronics/electronics.html Overview of requirements

3. 4 November 2002Paul Dauncey - Electronics3 Original proposed system 15 readout boards Each handles digitisation of 2 layers 1 trigger board Holds off further triggers until readout complete 1 test board (not shown) For testing cable connections of readout board Readout board most complex part Each cable handled by slave FPGA Whole board controlled by master FPGA

4. 4 November 2002Paul Dauncey - Electronics4 Conceptual Design Review, 11 Oct CDR was held on 11 Oct at RAL; four external reviewers Rob Halsall, Adam Baird (RAL), Greg Iles (IC), John Lane (UCL) Technically, design considered good: Overall concept thought sound and should be kept Minor issues and suggested improvements (see report) Cost estimate reasonable But schedule thought unrealistic: Loss of RAL ID effort since July impacted more than foreseen so schedule further behind than anticipated RAL drawing office for layout heavily booked (by LHC!) so unlikely to get effort when required N.B. extra three months to Mar 2004 already factored in at CDR

5. 4 November 2002Paul Dauncey - Electronics5 How to get back on schedule? Rob Halsall and Adam Baird negotiated 1 month RAL ID effort for themselves to work with us up to PPRP approval; they propose Taking an existing design with similar architecture Only rework the parts which have to be different Save layout and engineering effort of rest of board They will help us evaluate feasibility and resources required Suggest start from CMS Tracker Front End Driver (FED) Will be used to read out CMS silicon tracker CMS needs ~500 FEDs in final system Already taken ~10 man-years of design effort (IC and RAL) First full-specification prototypes due in Dec 2002

6. 4 November 2002Paul Dauncey - Electronics6 0V CMS Tracker FED Front End FPGA 12x Opto Rx PD Array 4x Prog Delay 1 Synch & Processing TTCrx VME QDR SSRAM 2 5V3.3V1.5V Dual ADC 3.3V Dual ADC 1 6 0V Front End FPGA 12x Opto Rx PD Array Synch & Processing 8 Dual ADC Dual ADC 43 48 Readout & Synch Control ASIC FPGA 12 1 1 Temp Sense Temp Sense 4x Prog Delay FPGA 1 3 4x Prog Delay FPGA 4x Prog Delay FPGA 22 24 Temp Sense 3.3V 1.5V 5V -5V spare PD Boundary Scan System ACE E-Fuse Hot swap DC-DC Back End FPGA Temp Sense 12x trim dac Buffer Jumper Matrix Compact Flash VME64x Interface FPGA Test Connector SW Hot swap cycle Live extract request Config E2PRO M Vref DAQ TTS Spare 1.5V 3.3 V 5.0 V 2.5V -5.0V 2.5V 96 85 Vref 1.5V Run/Halt VME Power Good LEDs extract Id E2 Prom FLT LEDs FSYNC Readout +12V LEDs +5V +3.3V FE 1 FE 8 EMU LEDs Process Transfer +2.5V LEDs +1.5V -5.0V halted LEDs Busy error TTC Over temp LEDs VME Clock Control Data Clock Control Data 8 3.3V1.5V

7. 4 November 2002Paul Dauncey - Electronics7 FED board compared to readout board Master  BE +VME; very similar Slave  FE; need to rewrite firmware ADCs, etc; totally different

8. 4 November 2002Paul Dauncey - Electronics8 Ideally, keep everything to the right, redo everything to the left Restricts readout board to same I/O and inter- FPGA paths as FED No show- stopper seen so far FED layout

9. 4 November 2002Paul Dauncey - Electronics9 FED is designed to operate in large system for many years High emphasis on reliability and operation efficiency Hot swap capability, multiple-level temperature cut-outs, etc. Way over-engineered for a beam test May not mount all components to save on cost FED FPGAs need much greater functionality than readout board FPGAs are much higher grade (and more expensive) FED VME FPGA can do VME64; doubles VME data rate FED size is 9U not 6U; cannot reduce without redoing layout 9U board more expensive; board cost £3k  £6k Bigger, so aim to get more cables per board; 6  16 Less boards needed; 15  6 9U crate also more expensive; £5k  £10k Only need one VME crate for whole system Other aspects

10. 4 November 2002Paul Dauncey - Electronics10 Trigger and test boards CMS take data out through non-VME backplane pins Custom data path as VME too slow Unused in readout board implementation Enough bandwidth to route trigger board signals into BE FPGA Aim to implement trigger board functions in part of BE All readout boards will be identical Select one slot for trigger functions to be turned on Saves engineering and layout for second PCB Still need to do firmware Most of FED debugged before used as readout board Testing much less of an issue Sophisticated board (£5k plus engineering) considered excessive Test board will be much simpler, less functional (£1k)

11. 4 November 2002Paul Dauncey - Electronics11 Cost, effort, schedule Cost needs careful evaluation; probably come out very close 9U and expensive FPGAs push it up Less boards and crates pull it down Effort needed from RAL estimated to be slightly higher Layout effort; 3 months, down from 4 Engineering effort; 15 months total, up from 12 Need engineer for duration of project; now goes to Mar 2004 Would be significantly higher without reusing FED design Implies underestimate originally, or insufficient progress over summer Schedule should fit into later end date of Mar 2004 Delayed first layout until Apr 2003, after LHC work Also gives more time for RAL engineer to get up to speed Reduced prototype test time from 6 to 5 months