1. Physically Aware HW/SW Partitioning for Reconfigurable Architectures with Partial Dynamic Reconfiguration Sudarshan Banarjee, Elaheh Bozorgzadeh, Nikil Dutt, University of California, Irvine Presented by Abhijeet Lawande

2. 2 Outline  Introduction  Target System Architecture  Placement Issues  Proposed Approach  Placement Example  Experimental Results  Conclusions

3. 3 Introduction  Hardware / Software Partitioning  Used in systems with reconfigurable hardware (FPGA) operated in conjunction with a software processor  Hardware and Software tasks can execute concurrently  Partitioning divides task graph into HW executed and SW executed tasks to reduce time to completion

4. 4 Introduction  Partial Reconfiguration  ‘Columns’ of FPGA can be configured independently  Hardware mapped to other columns continues to run during reconfiguration  Partial Dynamic Reconfiguration  Allows reuse of FPGA resources  However, feasibility of placement no longer guaranteed

5. 5 Target System Architecture  Software: A processor running software tasks  Hardware: An FPGA accelerator that supports partial reconfiguration  Shared Memory: Dedicated memory used to transfer input/output data between tasks General Purpose Memory Software Hardware (Partial RTR) Shared Memory

6. 6 Target System Architecture  Shared Memory can be implemented as on-chip or off- chip dedicated memory  Tasks mapped to the same device have negligible communication overhead  Tasks mapped to different devices incur a HW/SW communication overhead  Primary advantage: FPGA task placement reduces to simple linear placement

7. 7 Criticality of Task Placement  Each HW task occupies one or more adjacent FPGA columns  Placement feasibility in not guaranteed even with an exact algorithm  Infeasible implementation can result from scheduling conflicts if not considered during placement

8. 8 Criticality of Task Placement Infeasible Task Graph

9. 9 Criticality of Task Placement Feasible Task Graph

10. 10 Criticality of Task Placement Infeasible placement

11. 11 Heterogeneous Implementations  FPGA contain heterogeneous components:  Memory Blocks  Hardware Multipliers  Embedded Processors  Placement should consider multiple hardware implementations of tasks  Problem: Resources are limited and available in specific locations on FPGA

12. 12 Configuration Prefetch  Reconfiguration can take place as other HW tasks execute  Prefetch of configuration data should be considered while scheduling tasks

13. 13 Proposed Approach  Exact Algorithm: Integer Linear Programming  Technique of Optimization given linear constraints  Constraints: Traditional HW/SW partitioning + Contiguous placement + Configuration Prefetch  Implementation on commercial ILP solver (CPLEX) very slow  Heuristic Formulation:  Modified KLFM approach

14. 14 Basic KLFM Heuristic KLFM Loop: While (more unlocked tasks) select best task to switch between HW/SW move & lock best task update best partition if new partition is better

15. 15 Basic KLFM Heuristic KLFM Loop: While (more unlocked tasks) for (each unlocked task) for (each alternate implementation) calculate makespan by physically aware list scheduling select & lock best (task, implementation point) update best partition if new partition is better

16. 16 Placement Example Time C1 C2C5 C4 C3 C6 Proc 1 2 6 7 8 9 10 5 3 4 E1E1 E2E2 R3R3 R4R4 E3E3 E4E4 R5R5 E5E5 P6P6 C 65 Gap T1T1 T2T2 T3T3 T4T4 T5T5 T6T6 TaskHW time SW timeHW area 15233 2293 32112 43141 52102 6374

17. 17 Experiments on Feasibility Placement-unawarePlacement-aware TestT ILP FeasibilityT ILP T HEU tg110Y 11 tg525NO26 Mean-value21Y tg720Y tg1027NO2829 FFT25Y tg1136NO3841 tg1214NO1518 4-band eq27Y

18. 18 Case Study: JPEG Encoder  Resource constraint of 8 columns  Total area occupied by tasks: 11 columns  Data collected for a 256x256 color image ExperimentSchedule length (ms) HW-SW partitioning, no partial RTR16.74 HW-SW, partial RTR9.9 HW-SW, partial RTR, perfect prefetch9.04 Finer-grain graph7.21 Multiple implementations, single heterogeneous column 6.82 Best implementation points only9.58

19. 19 Conclusions  Current techniques do not consider one or more placement and scheduling issues:  Configuration prefetch  Feasibility of partition  Single reconfiguration controller bottleneck  Multiple Implementations  Heterogeneous Architecture  Integer Linear Programming: Exact solution, but very long run-time  Modified KLFM Heuristic: Almost ideal solution, run-time of minutes of hundreds of nodes

20. 20 References Physically-aware hw-sw partitioning for reconfigurable architectures with partial dynamic reconfiguration (2005) Physically-aware hw-sw partitioning for reconfigurable architectures with partial dynamic reconfiguration by S Banerjee, E Bozorgzadeh, N Dutt In DAC ’05: Proceedings of the 42nd annual conference on Design automation Hardware/software partitioning using Integer Programming (1996) Hardware/software partitioning using Integer Programming by R Niemann, P Marwedel In Proc. ED&TC http://www.cs.ucr.edu/~harry/classes_files/CS269_06/papers/DAC05/20- 2.ppt http://www.cs.ucr.edu/~harry/classes_files/CS269_06/papers/DAC05/20- 2.ppt

21. 21 Extras

22. 22 Issues in Placement  Resource bottleneck of a single reconfiguration controller  May not be possible to hide reconfiguration overhead for all tasks  Cannot apply rectangular packing algorithms due to gaps in schedule (caused by dependencies)

23. 23 EST Computation Algorithm find earliest time slot where task can be placed reconfig start = earliest time instant that space and controller are available together if (( reconfig start + reconfig time) < dependency time ) EST=earliest time parent dependencies are satisfied else EST=end of reconfiguration