1. 1 FTK AUX Design Review Functionality & Specifications M. Shochet November 11, 2014AUX design review

2. FTK Pixel & SCT data are organized in  -  towers by the Data Formatters and sent to the core crates (8). The data enters a core crate via the AUX card, an auxiliary (RTM) board sitting behind the pattern recognition board (AMB). November 11, 2014AUX design review2

3. November 11, 2014AUX design review3 9U × 280 mm auxiliary card (with the heat sinks removed)

4. AUX functionality Receive silicon hits in 5 SCT layers and 3 pixel layers from a Data Formatter on 2 QSFP+ fiber blocks. Convert each hit into the courser resolution (superstrip or SS) used in pattern recognition. Transmit the superstrips to the AMB on 12 serial links across the VME P3 connector (1 per SCT layer, 2 per pixel layer, 1 unused at present). Transmit each hit and the corresponding superstrip to the Data Organizer (DO), a smart database that stores the full resolution hits so that all hits associated with a single track pattern can be immediately retrieved. Receive on 16 serial links from the AMB across the P3 connector the addresses of patterns in which there were hits on the required number of layers (Road). November 11, 2014AUX design review4

5. AUX functionality (cont) For each road, carry out the track fitter (TF) function: –Try all combinations of 1 hit per silicon layer. –Carry out a linearized calculation of the goodness of fit (  2 ). –Allow 1 layer without a hit. –If there were hits on all layers, but the  2 is too large, refit dropping the hit in one of the layers. –Pass on track candidates that satisfy a  2 requirement. Pass all track candidates within a road through duplicate track removal (Hit Warrior or HW). –If 2 candidates share a programmable number of hits, keep the better track. Send the accepted track candidates to the Second Stage Board (SSB) on a SFP+ fiber. November 11, 2014AUX design review5

6. November 11, 2014AUX design review6 3 pixel layers, 1 SCT layer from DF Data Flow 4 SCT layers from DF Convert each hit into a SS using Input FPGA internal memory Send SS to AMB Send hit & SS to DO There are 4 processor FPGAs, each receiving roads from one AMB LAMB. Hits & SSs are retransmitted quickly using Altera’s Reverse Serial Loop- back capability. Road addresses sent from AMB Send tracks to HW in Input FPGA 2. Send tracks to SSB

7. November 11, 2014AUX design review7 Serial link data rates: WH 70 pile-up MC (80 pile-up with full wildcard usage to be produced) Specification Tested to BER<10 -15 < 2 Gbps 6 Gbps 6.4 Gbps < 0.6 Gbps 2 Gbps < 2 Gbps 6 Gbps 6.4 Gbps < 0.85 Gbps 2 Gbps 1.2 Gbps 6 Gbps 6.4 Gbps 2 Gbps 6 Gbps 6.4 Gbps

8. Processing Rate Requirements The input FPGAs convert full resolution hits to SSs and carry out the HW function. Both of these can be done at the full data transfer rate, so they are not limitations. The challenge is in the processor FPGAs, both the DO and TF functions. Data Organizer: –The expected number of hits for a 70 pile-up WH event is < 650 per layer, or 1 hit per 15 ns. (The 8 layers are handled in parallel.) –The specification is 1 hit per 5 ns. –The expected rate of roads from the AMB into a processor chip is < 800/event, or 1 road per 13 ns. –The specification is 1 road per 5 ns. Track Fitter: –The expected number of fits in a processor chip per event is < 6000, or 1 fit per 1.7 ns. –The specification is 1 fit per 1 ns. November 11, 2014AUX design review8

9. Following talks Board design, prototype history, and power usage – Mircea Bogdan Firmware and testing – John Alison November 11, 2014AUX design review9