1. The Fast Tracker Real Time Processor ACES workshop, 9-11 March 2011 CERN - Geneva, Switzerland
FTK poster
F. Crescioli
Alberto Annovi
for the ATLAS collaboration and FTK group
Istituto Nazionale di Fisica Nucleare
Laboratori Nazionali di Frascati

2. Fast tracking in pixel and SCT det.
Total # of readout channels:
PIXELS: 80 millions
SCT: 6 millions
+ IBL: 6 3cm
A. Annovi - ACES CERN

3. Two time-consuming jobs in tracking: Pattern recognition & Track fitting
Pattern recognition – find track candidates with enough Si hits
109 prestored patterns (roads) simultaneously see the silicon hits leaving the detector at full speed.
Based on the Associative Memory chip (content-addressable memory) initially developed for the CDF Silicon Vertex Trigger (SVT).
A. Annovi - ACES CERN

4. Track fitting – high quality helix parameters and 2
Over a narrow region in the detector, equations linear in the local silicon hit coordinates give resolution nearly as good as a time-consuming helical fit.
pi’s are the helix parameters and 2 components.
xj’s are the hit coordinates in the silicon layers.
aij & bi are prestored constants determined from full simulation or real data tracks.
The range of the linear fit is a “sector” which consists of a single silicon module in each detector layer.
This is VERY fast in FPGA DSPs.
14D coord. space
5D surface
Nucl.Instrum.Meth.A623: ,2010
doi: /j.nima
A. Annovi - ACES CERN

5. Feeding FTK @ 100kHz event rate
ATLAS Pixels + SCT
Divide into
more than 2 sectors
1/2 f AM
Allow a small overlap
for full efficiency
1/2 f AM
8 buses 100MHz/bus
Up to 8 Logical Layers: full h coverage
8 f regions each with
8 sub-regions (h-f towers)
df~22.5o, dh~1.25
bandwidth for up to
3×1034 cm-2s-1
A. Annovi - ACES CERN

6. System overview
LVL1 output
100 kHz
Event rate
Processing unit (2/tower)
HLT farm
Highly parallel data flow: 64  - towers in 8 core crates and 8-fold parallelism within each tower (for inst. lum. 3×1034)
Second stage: extrapolate into stereo SCT layer. Include stereo hits in final fit.
A. Annovi - ACES CERN

7. Data Flow in FTK (goals)
Designed for 100kHz input event rate and 40 pileup events
Parameters tuned for 75 pileup events (3×1034) to provide safety margin
~300 S-Link inputs (with IBL) ~400Gbit/s
Input hit rate at each Processing Unit 8*100 MHz hits
128 PU: max total hit input rate 100GHz
Max output roads/board 800MHz
Max Total 100 GHz roads
Max Track Fitting rate 4GHz/board
Max Total 500 GHz fits
Total Track rate after 1st step 640MHz
Track fitting performs first data reduction!
2nd step final output ~300 tracks / 3e34
The full FTK system size is 7 racks
Note: rates are word rates for hits, roads and tracks
A. Annovi - ACES CERN

8. FTK input connection 1st output 2nd output
Dual output HOLA on SCT/Pixel RODs
1st output
2nd output
FTK clustering mezzanine on Data Formatter
Duplicate ROD outputs
Up to 4 S-Link inputs (Pixel and SCT)
Clustering 1 or 2 pixel inputs
Clustering time linear with occupancy:
scales with luminosity
A. Annovi - ACES CERN

9. The algorithm working principle
FPGA replica of pixel matrix
Core logic:
Hit associated into clusters
Load all
module hits
select
left most
top most hit
NIM A617: ,2010
propagate
selection
through cluster
Loop over clusters in a module
Eta direction -->
and pixel modules
Loop over events
1st phase:
The pixel module is a 328x144 matrix.
Replicate a part of it (8x164) in hw matrix.
The matrix identifies hits in the same cluster (local connections).
2nd phase:
Hits in cluster are analyzed (averaged).
Flexibility to choose algorithm!
read out
cluster
2nd pipeline stage
Average
calculator
high level cluster analysis
out
A. Annovi - ACES CERN

10. Data Formatter block diagram
Bundle of 12 fibers
each running up to
3.5Gpbs
SNAP12 links
FPGAs
or high speed fibers
The DF core are 1 or a few FPGA distributing ~10Gbps of data to the appropriate outputs
A. Annovi - ACES CERN

11. Procrocessing Unit CDF AMBoard with 4 LAMBs
Pattern recognition & track fitting condensed in a single 9U board + aux card.
Allows for highly parallel architecture.
Hit database (DO)
Track fitter
Duplicate Removal (HW)
Pattern recognition with Associative Memory
128 AM chip on a single board
CDF AMBoard
with 4 LAMBs
SNAP12 link
A. Annovi - ACES CERN

12. Which banks we would like to have
   
What we have now: Standard Cell nm
pattern/chip for 6-layer patterns,
2500 pattern/chip for 12-layer patterns
“A VLSI Processor for Fast Track Finding Based on Content Addressable Memories”,
IEEE Transactions on Nuclear Science, Volume 53, Issue 4, Part 2, Aug Page(s):
65 nm technology provides a factor → patterns/chip
Full custom cell provides at least a factor 2 → patterns/chip
8 layers instead of 12 provides a factor 1,5 → patterns/chip
1,2 x 1,2 cm^2 2D chip → patterns/chip
With a 2 D chip we gain a factor 30!
1 AMboard: 128 chips → ~10 Mpatterns per board
1 Crate: 16 AMboard → ~160 Mpatterns per crate
Current prototype under design:
65nm TSMC, 12mm^2 MPW run, 100 MHz running clock
8000 patterns/chip 8 layers each
Layer words of 12 bits + 3 ternary bits  variable resolution patterns
NEXT:
NEW
VERSION
For both L1 & L2
A. Annovi - ACES CERN

13. Pattern efficiency Pattern size r-f: 24 pixels, 20 SCT strips
z: 36 pixels
Pattern size (half size)
r-f: 12 pixels, 10 SCT strips
z: 36 pixels
90%
65M
500M
Want this
# of patterns in Amchips (barrel only, 45 f degress)
<# 3E34> = 342k
<# 3E34> = 40k
A. Annovi - ACES CERN

14. Variable resolution AM
We can use don’t care on the least significant bit when we want to match the pattern carser resolution or use all the bits to match finer resolution
coarser pattern
gain an effective factor of 5 in patterns
With 2 “don’t care” bits per layer
finer patterns
coarser
pattern
Patterns with 1 kid are stored at finer precision
Layers without “don’t care (DC)” can ignore the hits in the “wrong” side of the layer DC
A. Annovi - ACES CERN

15. Goal: x30 pattern density but lower power consumption
32 patterns of 8 layers ~ 60mm x 500mm ~ 1 or 2 pixels
A. Annovi - ACES CERN

16. Conclusions
Several technological challenges and solutions (in progress)
Working to define initial FTK system
Preparing FTK prototypes
2012 First prototype test with data
2014 Barrel only FTK system
2016 Full FTK system
See FTK poster F. Crescioli
A. Annovi - ACES CERN