1. 1 Design Issues of Flash-based SSD& Hybrid Disks Han-Lin Li Dept. Computer Science and Information Engineering National Taiwan University Advisor: Prof. Chia-Lin Yang

2. 2 Outline Background NAND vs. NOR Organization and characteristics of NAND flash memory Trend of NAND flash memory technology Design Issues of Flash-Based SSD FTL design Efficient garbage collection Wear-leveling techniques Multi-Chip (bank) flash memory Flash memory as a swap device of virtual memory Design Issues of Hybrid Disk Our current work

3. 3 Multi-Chip(bank) Flash Memory Use stripping and interleaving techniques to improve performance (RTAS’02) Bank 1 Bank 2 Sub- request Sub- request Bank 1 Bank 2 Request 1 Request 2 Stripping example Interleaving example

4. Flash memory as a Swap Device of Virtual Memory Replacement policy design (CASES’06, CODES+ISSS’06) Subpaging (ISLPED’06) HotCache (ISLPED’06) Duplication-Aware Garbage Collection (TVLSI’08)

5. Clean-First LRU The cost of swapping out a dirty page is much higher than swapping out a clean page Splits the LRU list into Working region Clean-first region Selects a clean page to evict in the clean-first region first to save flash write cost

6. OneNAND XIP To reduce # of page faults On page fault Only load frequently used code page to main memory Infrequently used code page use eXecution In Place (XIP) How to identify frequently used code page? If # of occurrences of the missed page in the page history window > a predefined threshold  Frequency used code page

7. Subpaging Divide a virtual memory page into a set of subpages in the granularity of flash page size Each subpage is associated with a dirty bit. Memory Page Clean Data Dirty Data Clean Data One Write to Flash Flash Page Size 0 1 0 0 Dirty Bit Flash Memory

8. HotCache Flash Memory Physical device FTL layer Command translation MTD layer (f, 0, 0, 3) 1(f, 0, 1, 2) 2(s, -, 2, -) LBA Physical address (f/s, bank, block, page) ………… address translation table 0 HotCache Management Garbage Collection HotCache Caching writes only Preserving intra-page locality Capturing hot data

9. D D D D D D D D C C C C C C C C B B B B B B B B Flash pages in one main memory page are written to flash memory back to back A0A0 A1A1 A2A2 A3A3 A4A4 A5A5 A6A6 A7A7 B0B0 B1B1 B2B2 B3B3 B4B4 B5B5 B6B6 B7B7 C0C0 C1C1 C2C2 C3C3 C4C4 C5C5 C6C6 C7C7 D0D0 D1D1 D2D2 D3D3 D4D4 D5D5 D6D6 D7D7 Block XBlock Y A0A0 A1A1 A2A2 A3A3 A4A4 A5A5 A6A6 A7A7 Virtual page Main memory A 0, A 1, A 2, A 3, A 4, A 5, A 6, A 7 Swap_out(A) What is Intra-page Locality?

10. After page A, B are swapped out AAAA AAAA AAAA AAAA BBBB BBBB BBBB BBBB CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD Block XBlock YBlock XBlock Y Block X Block Y Block X Block Y It affects the efficiency of garbage collection Why is Preserving Intra-Page Locality Important?

11. D D D D 1 D D D D 1 Exploit data redundancy between the main memory and flash memory to eliminate unnecessary live page copying during garbage collection An invalided page A free page Duplication- Aware Garbage Collection 0 B B B B A A A A Main Memory 0 Dirty Bit Flash Memory AAAA BBBB CCCC CCCC D D D D 1 D D D D 11 B B B B A A A A Main Memory 1 Dirty Bit Duplication-Aware Garbage Collection

12. Design Issues of Hybrid Disk Using NAND flash as disk cache Issues Saving power Improving performance Improving endurance

13. Saving Disk Power by Flash Cache Disk is a big energy consumer in mobile systems Can we reduce disk power? If the disk is idle, we can change it to power saving mode But the disk idle time may be less than the break even time Could we extend the disk idle time?  Caching could reduce disk access  Prefetching can move disk access time forward  Write buffering can move disk access time backward The energy consumption parameters for the Hitachi-DK23DA hard disk. Disk access address time Caching Prefetching Write buffering Disk idle time

14. Our Current Works Improve endurance through bit inversion Improve performance through parallel garbage collection in a multi-bank flash system

15. Our Current Works Improve endurance through bit inversion Improve performance through parallel garbage collection in a multi-bank flash system

16. Improving Endurance Probability to damage a flash cell should be proportional to # of charge loss/gain in floating gates Only writing 0 or erasing a cell containing 0 will charge/discharge a floating gate We may reduce # of “0” writes to improve flash life time Stored electrons Erased = “1”Programmed = “0” Control Gate Floating Gate Substrate DrainSource Tunnel Oxide

17. Bit Inversion If more than ½ bits in an inversion unit = 0 Invert all bits in the inversion unit Set flag = 1 Advantage Reduce # of 0 writes Disadvantage Additional bit write & space requirement Additional write is negligible (<0.1%) Put flag in spare area 1000010100111011 011110100011101110 Inverted data Flag Original data Inversion Unit 5*“0” 3*”1”3*“0” 5*”1”

18. Bit Inversion When data are written to flash Data will be stored in SRAM temporarily “0” counter count # of “0” in each inversion unit Data will be written to flash latter after “write allocate” If # of “0” in an inversion unit > threshold,  Invert all bits in the inversion unit  Set flag of the inversion unit = 1 When data are read from flash Read data from flash to SRAM If the flag of an inversion unit = 1  Invert all bits in the inversion unit Flash Memory Controller Flash Interface Inversion Logic CPU Core Host Interface “0” Counter SRAM System Bus Flash Memory Chips Flash Memory Bus Host Interface

19. # of 0 in different unit size in files Test case 1 : a MS word file Test case 2 : a JPEG file 2KB 512B Smaller inversion unit size => larger opportunity to reduce # of “0” writes

20. Parallel Garbage Collection Parallel live page copying to improve performance Copy live pages to different bank/chip Write live data Victim block Buffer Read live data Flash Chips Flash blocks Erase the block Read live dataWrite live data Erase the block Flash Chips Read live page1Write live page1Erase the block Chip 1 Read live page1Erase the block Chip 1 Write live page1 Chip 2

21. Reference Park, S., Jung, D., Kang, J., Kim, J., and Lee, J. 2006. CFLRU: a replacement algorithm for flash memory. In Proceedings of the 2006 international Conference on Compilers, Architecture and Synthesis For Embedded Systems (Seoul, Korea, October 22 - 25, 2006). CASES '06. ACM, New York, NY, 234-241 Energy-Aware Flash Memory Management in Virtual Memory System,L.-H. Lin, C.- L. Yang, H.-W., Tseng, to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems An adaptive striping architecture for flash memory storage systems of embedded systems, L.-P. Chang and T.-W. Kuo, RTAS’ 02 Joo, Y., Choi, Y., Park, C., Chung, S. W., Chung, E., and Chang, N. 2006. Demand paging for OneNAND™ Flash eXecute-in-place. In Proceedings of the 4th international Conference on Hardware/Software Codesign and System Synthesis (Seoul, Korea, October 22 - 25, 2006). CODES+ISSS '06. ACM, New York, NY, 229- 234. An Energy-Efficient Virtual Memory System with Flash Memory as the Secondary Storage, H.-W. Tseng, H.-L. Li, and C.-L. Yang, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '06), Tegernsee, Germany, October, 2006 Chen, F., Jiang, S., and Zhang, X. 2006. SmartSaver: turning flash drive into a disk energy saver for mobile computers. In Proceedings of the 2006 international Symposium on Low Power Electronics and Design (Tegernsee, Bavaria, Germany, October 04 - 06, 2006). ISLPED '06. ACM, New York, NY, 412-417.

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