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1 Design Issues of Flash-based SSD& Hybrid Disks Han-Lin Li Dept. Computer Science and Information Engineering National Taiwan University Advisor: Prof.

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Presentation on theme: "1 Design Issues of Flash-based SSD& Hybrid Disks Han-Lin Li Dept. Computer Science and Information Engineering National Taiwan University Advisor: Prof."— Presentation transcript:

1 1 Design Issues of Flash-based SSD& Hybrid Disks Han-Lin Li Dept. Computer Science and Information Engineering National Taiwan University Advisor: Prof. Chia-Lin Yang

2 2 Trend of Flash Memory Application Machine size Cell PhonePDANotebookServer Solid State Drive Single Chip Hybrid Disk Low Power Small Size Reliability Low Power Performance Reliability Low Power Performance Reliability Small Size Requirement Sensor Node Low Power Small Size

3 3 Outline Background NAND vs. NOR Organization and characteristics of NAND flash memory Trend of NAND flash memory technology Design Issues of Flash-Based SSD FTL design Efficient garbage collection Wear-leveling techniques Multi-Chip (bank) flash memory Flash memory as a swap device of virtual memory Design Issues of Hybrid Disk Our current work

4 NAND vs. NOR NOR Design for storing program code Needs random-access for reading Rarely needs to be updated Cells are connected in parallel to the bit lines Allowing cells to be read and programmed individually NAND Goal of NAND flash was to replace hard disks Reduce chip area required to implement a given capacity  Reduce cost per bit  Increase maximum chip capacity Cells are connected in series Cells connected in series must be read in series Occupy only a small fraction of the area of equivalent NOR cells

5 NAND vs. NOR NOR[19]NAND[20] Read/Write UnitWord(2B)2KB Block size16K/64K128K Read latency110ns25µs Write latency100µs200µs Erase time0.6s2ms CostExpensiveCheap

6 6 Organization of a Typical NAND Flash Memory NAND Flash Cell Single-level Cell (SLC) 1 bit/Cell Level 0 = Erased “1” Level 1 = Programmed to “0” Multi-level Cell (MLC) 2 bits/Cell Level 0 = Erased “11” Level 1 = Programmed to “10” Level 2 = Programmed to “01” Level 3 = Programmed to “00” Voltage Distribution Voltage 1 0 Distribution SLC MLC Control Gate Floating Gate Substrate DrainSource Tunnel Oxide Stored electrons Erased = “1”Programmed = “0”

7 7 Organization of a Typical NAND Flash Memory NAND Flash Cell Potential problem Endurance  Flash has limited write/erase times Data retention  Stored electrons lost due to leakage Control Gate Floating Gate Substrate DrainSource Tunnel Oxide

8 8 … Block 0 Block 1 Block 2 Block 3 Erase one block … Read/Write one page 1 Page Organization of a Typical NAND Flash Memory Samsung K9F1208R0B 1 Block = 32 pages 1 Page = 512B

9 9 Flash Memory Characteristics Write once Written page can not be overwritten Flash Memory Flash block A free page

10 10 Flash Memory Characteristics Write once Written page can not be overwritten A Flash Memory A live page A free page Live page Flash block

11 11 Flash Memory Characteristics Write once Written page can not be overwritten Out-place update A’ Flash Memory A live page A dead page A free page Dead page New data Flash block

12 12 Flash Memory Characteristics (cont’d) Garbage collection When # of free pages < GC t ( Garbage Collection Threshold ) Erase a block to reclaim dead pages Flash Memory Flash block A live page A dead page A free page

13 13 Flash Memory Characteristics (cont’d) Flash Memory Flash block A live page A dead page A free page Garbage collection When # of free pages < GC t ( Garbage Collection Threshold ) Erase a block to reclaim dead pages

14 14 Flash Memory Characteristics (cont’d) Garbage collection When # of free pages < GC t ( Garbage Collection Threshold ) Erase a block to reclaim dead pages Overheads Live data copying Block erase Flash Memory Flash block A live page A dead page A free page

15 15 Flash Storage System Architecture Physical device File Translation Layer (FTL) Command translation MTD layer Logic Block Address Physical address Flash Memory (0, 0, 3) 1(0, 1, 2) 2(1, 2, 1) LBA Physical address (bank, block, page) ………… address translation table 0 Garbage Collection

16 16 Trend of Flash Memory Technology As VLSI technology continues to scale, Advantage Capacity ↑ Disadvantage Data retention ↓  The floating gate is smaller  # of electrons in floating gate ↓  The tunnel oxide is thinner  Leakage current ↑ Endurance ↓  The tunnel oxide is thinner  Write/Erase operations damage oxide more easily Control Gate Floating Gate Substrate DrainSource Tunnel Oxide NAND Flash- SLC(μm 2 /bit) NAND Flash- MLC(μm 2 /bit) ITRS 2007 roadmap for memory technology.

17 17 Trend of Flash Memory Technology Multi-Level Cell (MLC) flash Advantage Capacity ↑ Disadvantage Data retention ↓  Voltage gap between each state is smaller Voltage Distribution Time Voltage Distribution Voltage Distribution Time Voltage Distribution SLC MLC Control Gate Floating Gate Substrate DrainSource Tunnel Oxide

18 18 Trend of Flash Memory Technology Page/Block size increasing [3] Latency ─ Throughput ↑ Operation512B-page2KB-page Read (page)15 us25us Write (page)200 u s Erase (block)2 ms Latency of operation in different flash page size [4,5]

19 19 Design Issues of Flash-Based SSD FTL design Reduce FTL’s memory requirement Efficient garbage collection Reduce garbage collection overhead Wear-leveling techniques Prevent blocks from being unevenly worn so as to lengthen the overall lifespan

20 20 FTL (File Translation Layer) Map logical address to physical address to simulate traditional disk FTL granularity How many LBAs associated with an entry of FTL FTL granularity ↑ Smaller FTL table size Larger update overhead AB CD Block X A’ Block Y FTL granularity = 1 page Update page A AB FTL AB CD Block X A’ Block Y FTL granularity = 2 page Update page A BAB FTL

21 FTL (File Translation Layer) (cont.) Dynamic switch between fine-granularity and coarse-granularity in the FTL [7] Exploit the advantages of fine-grained FTL and coarse-grained FTL Switch to fine-grained FTL when out-place update triggered  Reduce update overhead Switch to coarse-grained FTL when # of entries in fine-grained FTL exceeds limit  Limit FTL table size  LRU replacement policy AB CD Block X A’ Block Y Update page A AB FTL Address Translation Table A Fine-Grain Hash Table A Coarse-Grain Hash Table

22 FTL (File Translation Layer) (cont’d) Multi-level FTL [6] Some LBAs are never used Don’t create FTL entries for unused LBAs in Multi-level FTL Save memory spaces

23 23 Efficient Garbage Collection Objective Reduce garbage collection overhead (# of live page copies) Cost-benefit policy [16] Choose the block of the largest score calculated by age: the time past since last modification of the block u: the live pages in the block Hot-cold separation [10] High # of write operation => hot data Low # of write operation => cold data Put hot data in the same block can reduce garbage collection overhead H H H H HH Block X HH CC CC CC CC After hot data are rewritten Block X CC CC CC CC H C Hot data Cold data Dead page

24 Wear-Leveling Techniques Principle #1 Allocate hot data to blocks with fewer erasure cycles Principle #2 At garbage collection, choose a block with fewer erasure cycles as the victim block

25 Wear-Leveling Techniques Hot-Cold Swapping [8] Periodically check If the difference between the erasure cycles of the oldest block and the youngest block > threshold  Data stored in the oldest block and in the youngest block are swapped. Static-Dynamic [17] Static: Hot-cold swapping Dynamic: Blocks are allocated for new writes from a round-robin queue that sorts blocks in terms of their physical block addresses

26 Wear-Leveling Techniques CAT [14] When garbage collection, always erase the block of the minimal score calculated by formula μ i : The space utilization of block i ε i : The erasure cycle of block i. a i : age of block i.

27 27 References 1. Energy-Aware Flash Memory Management in Virtual Memory System,L.-H. Lin, C.-L. Yang, H.-W. Tseng, to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2. Improving NAND Flash Based Disk Caches, T. Kgil, D. Roberts and T. Mudge, ISCA’ Future Outlook of NAND Flash Technology for 40nm Node and Beyond, K. Kim and J. Choi, NVSMW’ Samsung Electronics CO.,LTD. Datasheet of Samsung K9F1208R0B NAND flash, Samsung Electronics CO.,LTD. Datasheet of Samsung K9K2G08X0A NAND flash, A superblock-based flash translation layer for NAND flash memory, Kang, J., Jo, H., Kim, J., and Lee, J, EMSOFT '06 7. An adaptive two-level management for the flash translation layer in embedded systems, C.-H. Wu, T.-W. Kuo, ICCAD’06 8. Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design, Chang, Y., Hsieh, J., and Kuo, T., DAC’ On Efficient Wear Leveling for Large-Scale Flash-Memory Storage Systems, L.-P. Chang, SAC’ An adaptive striping architecture for flash memory storage systems of embedded systems, L.-P. Chang and T.-W. Kuo, RTAS’ Energy-aware demand paging on NAND flash-based embedded storages, C. Park, J.-U. Kang, S.-Y. Park, and J.-S. Kim., ISLPED’ SWL: a search-while-load demand paging scheme with NAND flash memory, J. In, I. Shin, H. Kim, LCTES’ SmartSaver: turning flash drive into a disk energy saver for mobile computers, Chen, F., Jiang, S., and Zhang, X., ISLPED’ Using Data Clustering To Improve Cleaning Performance For Flash Memory, M. L. Chiang, Paul C. H. Lee, and R. C. Chang, Software - Practice and Experience, An Effective Flash Memory Manager for Reliable Flash Memory Space Management, H. J. Kim and S. G. Lee, IEICE Transactions on Information and System, A flash-memory based file system., A. Kawaguchi, S. Nishioka, and H. Motoda., In Proceedings of the 1995 USENIX Technical Conference, pages 155–164, January M-Systems, TrueFFS Wear-Leveling Mechanism“ 18. Wear Leveling in Single Level Cell NAND Flash Memories," STMicroelectronics Application Note (AN1822), Samsung K8C1215EBM 20. Samsung K9F1G08R0A

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