1. 1 DØ RunIIb Trigger Upgrade: Status Darien Wood for the DØ Trigger Upgrade Group

2. D0 PMG 16-Nov-2004 2 Trigger System Upgrades CAL c/f PS CFT SMT MU FPD L1Cal L1PS L1CTT L1Mu L1FPD L2Cal L2PS L2CTT L2STT L2Mu Global L2 Framework Detector Lumi Level 1 Level 2 7 MHz2.5 kHz1 kHz L3/DAQ Level 3 <100 Hz Cal-TRK MU-TRK New (or replaced) System Enhanced System

3. D0 PMG 16-Nov-2004 3 L1Cal Trigger Status ADF v.2 layout complete, lining up vendors for pre- production run Orders placed for all remaining TAB and GAB components. Production readiness review was October 7 – now in production SCLD prototype has been used successfully in integration tests. Final board has successfully passed bench tests at Saclay Production track match card fabricated and assembled, loop test established ADC+Digital Filtering Clustering Global Sums & Topological Finished 05/03

4. D0 PMG 16-Nov-2004 4 L1Cal Trigger Status ADF v1 TAB GAB VME/SCL ADF v2 SCLD

5. D0 PMG 16-Nov-2004 5 L1 Cal progress since Sep 7: ADF  ADF v.2 layout completed u gerber files, layout & assembly instructions completed u negotiations with three vendors for fabrication and assembly s 1 st closed business s 2 nd finally declined order s 3 rd (ADCO) in progress u goal is to complete 10 pre-production modules in next few weeks

6. D0 PMG 16-Nov-2004 6 L1 Cal progress since Sep 7: TAB & GAB  Continued firmware work at Nevis u automated facility bit-by-bit comparison of simulated events u simple list of L1cal trigger terms implemented in GAB  ECL output receiver test card  Successful production readiness review Oct 7 th at Nevis u committee: Bob Hirosky (chair), Iain Bertram, Dan Edmunds, Joel Steinberg u recommendation to go ahead with production, using existing PCB’s: no modifications required u also examined installation commissioning plans and had many useful technical discussions  Assembly orders are now being processed at Columbia

7. D0 PMG 16-Nov-2004 7 L1 Cal progress since Sep 7: BLS cables and test stand area  UIC and Fermilab working on constructing a 5% system of transition cables/panels/paddles from existing BLS cables to ADF back planes  Impedance matching studies with prototypes  Mock-up of mechanical system and cable routing

8. D0 PMG 16-Nov-2004 8 Current BLS Cables Layout  How the BLS cables are set. 6.5‘‘ Rack Door We have decided not to move the cables

9. D0 PMG 16-Nov-2004 9 Mock-up We reproduce the current BLS cable layout for 128 BLS cables to test the design and to optimize the procedure to connect the cables

10. D0 PMG 16-Nov-2004 10 L1Cal Commissioning  Signal splitters allow digital filter and entire readout chain to be tested with full system prior to installation  Currently: u TAB data transmission to L2 and L3, tests of data unpacking u cable tests for inputs u patch panels/paddle cards for installation in hand u cable layouts defined Current L1cal (10 racks) Framework, L2, etc. Clock Upgrade rack(s) Comp uters Power, ground Split signals Serial command linkGround isolation Movable Counting House “Sidewalk”  Future: u Collect single-tower data to tune MC u Test trigger generation with real data u Full system will be installed on sidewalk

11. D0 PMG 16-Nov-2004 11 L1CalTrack Trigger Overview

12. D0 PMG 16-Nov-2004 12 Progress since Sep 7: L1 Cal-track match  Production MTCxx cards fabricated u will be sent for assembly shorty  Layout completed for production UFB: u will be sent for fab in next few days  Collision hall work completed u termination of long-haul cables completed u ready for pre-commissioning after end of shutdown Universal Flavor board (daughter) MTCxx (mother board)

13. D0 PMG 16-Nov-2004 13 L1 Central Track Trigger  Level 1 Central Track Trigger (CTT) essential for electrons, muons, taus (WH  l jj), input for STT vertexing trigger  Tracking trigger rates very sensitive to occupancy  Upgrade stategy: u Narrow tracker roads by using individual fiber hits (singlets) rather than pairing adjacent fibers (doublets) u Cal-track matching DFEA mother/daughter board redesigned as a single board (DFEB), with larger FPGA’s: (Xilinx Virtex-II XC2V6000)

14. D0 PMG 16-Nov-2004 14 Scope of Upgrade L1CTT  Original idea was to simply replace FPGAs to newer larger ones that allow more equations  Have recently upscoped the project to allow monitoring and debugging capability  The project now involves replacing two crates of electronics and the crates themselves  All elements in this upgrade have been designed to minimize commissioning time and simplify debugging

15. D0 PMG 16-Nov-2004 15 L1CTT progress since Sep 07: DFEA & Crate Controller  Combined DFEA motherboard-daughterboard u 2 complete boards (at Boston and Fermilab) u Boston: test data injection and capture features successfully tested s Remaining: commission SLDB receiver u Fermilab: installed on platform  Crate Controller u working well with DFEA on BU test stand u eight boards back from B.E.S.T. after BGA and QFN reflow u Will be assembled as production boards

16. D0 PMG 16-Nov-2004 16 L1CTT progress since Sep 07: crates and platform slice  Fully assembled DFE subrack installed in PW02 (on platform in collision hall) u power supplies u cables u inspection u ORC on Oct 26 th (can run unattended)  testing DFEA/M in situ u initializes OK – no problems u output fed to 9 th CTOC card u testing status bits

17. D0 PMG 16-Nov-2004 17 L1CTT parallel chain MixerDFEA crates (current) CTOC, etc Fiber signals LVDS splitters Partial prototype DFEA crate (upgrade) Prototype crate controller (upgrade) PC link Trigger framework timing (Serial command link) All elements of parallel slice of upgrade prototypes installed in Fall 04 shutdown Extra CTOC, CTTT

18. D0 PMG 16-Nov-2004 18 L1CTT Hardware New L1CTT Crate, Crate Controller, DFEB New DFE Crate backplane DFEB in new crate installed on the platform in DØ DFEB in stand-alone test setup with LVDS signals input

19. D0 PMG 16-Nov-2004 19 STT and Level 2  STT u Additional production of the same boards is needed to accommodate new Layer 0 channels u Production Readiness Review Friday Sept 10: s Buffer controller now in production s option of building additional Track Fit Cards awaiting final decision  Level 2 u Work in July/August to get the Concurrent Tech cPCI CPU to work with the 9u motherboard u Fallback CPU: Adlink cPCI-6860A u upgrade to proceed adiabatically Should be “transparent” upgrades

20. D0 PMG 16-Nov-2004 20 RunIIb Trigger Simulation/Algorithms  L1Cal u variety of small variations of sliding window algorithm studied for EM triggers u now improving upon RunIIa L1+L2EM performance u Prototype firmware versions of EM, Jet, and tau algorithms  L1CTT u Run IIa simulation package being restructured s will be much more easily adapted to Run IIb u Firmware being tested W->eν MC Greg Pawloski, Sabine Lammers Single EM

21. D0 PMG 16-Nov-2004 21 RunIIb Trigger Simulation/Analysis  Primary goal is “strawman” trigger list by early 2005 incorporating new algorithms u starting with current L2 trigger terms as a basis  “trigger rate tool” adapted to implement sliding windows algorithms u uses real collider data as input u accounts for correlations and combined rates of full trigger list  Closer coordination of effort between u Trigger Upgrade Project (coding new algorithms) u Trigger Board (policy) u Trigger Steering Committee (technical) u (new) Trigger Studies Group (physics/rate studies) u N. Varelas appointed Trigger Coordinator

22. D0 PMG 16-Nov-2004 22 CTT Manpower  Recommendation from July Director’s review: “Secure the manpower for all installation needs in the 2004 shutdown to allow testing during the data taking in FY05” u Additional engineering & technical help obtained for CTT. u Additional postdoc for CTT is highest priority

23. D0 PMG 16-Nov-2004 23 Triggers Summary  L1cal u ADF v.2 layout finished – 10 boards to be produced u continued progress in BLS cable transition u TABs and GABs cleared for production in PRR  L1caltrack u production MTCxx heading for assembly u production UFB heading for fabrication  L1CTT u Ongoing tests of DFEA/M, Crate Controller, and backplanes – all look good so far u complete parallel chain installed in CH during shutdwon  L2 u new candidate SBC being evaluated for L2beta u STT PRR completed, decision about production soon  Simulation u Cal EM algorithm being finalized, coded u More extensive combined simulations with real data

24. D0 PMG 16-Nov-2004 24 Backups

25. D0 PMG 16-Nov-2004 25 Management structure WBS 1.2: Trigger Upgrade P. Padley (Rice), D. Wood (Northeastern) WBS 1.2.1: Level 1 Calorimeter M.Abolins(MSU), H.Evans(Columbia) WBS 1.2.2: Level 1 Cal-track match K. Johns (Arizona) WBS 1.2.3: Level 1 Tracking M. Narain (Boston), Don Lincoln (FNAL) WBS 1.2.4: Level 2 Beta upgrade R. Hirosky (Virginia) WBS 1.2.5: Level 2 STT upgrade U. Heintz (Boston) WBS 1.2.6: Trigger Simulation M. Hildreth (ND), E. Barberis (NEU) WBS 1.2.7: AFE upgrade (Pending) A. Bross (FNAL) Project is largely university based

26. D0 PMG 16-Nov-2004 26 Upgrade L1 Cal: Major features  Calorimeter trigger upgrade u sharpens turn-on trigger thresholds u more topological cuts  Largest subproject in the trigger upgrade  Will require removing the existing Cal trigger

27. D0 PMG 16-Nov-2004 27 L1 CalTrack: Major features  Exploit new L1Cal trigger  Improve Run IIa  matching granularity x8  Needed in triggers for Higgs searches  electrons in WH and H  W * W modes  taus in H   and H +   Fake EM rejection is improved by ~x2  Fake  rejection is improved by ~x10  Very modest upgrade modeled on existing Mu-Track match system u Very few changes with respect to Mu-Track