1. UC San Diego / VLSI CAD Laboratory Learning-Based Approximation of Interconnect Delay and Slew Modeling in Signoff Timing Tools Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath and Jyoti Wadhwani VLSI CAD LABORATORY, UC San Diego 15 th ACM/IEEE System-Level Interconnect Prediction Workshop June 2 nd, 2013

2. -2- Outline Motivation Motivation Learning-based Interconnect Modeling Learning-based Interconnect Modeling Correlation Methodology with Signoff Timer Correlation Methodology with Signoff Timer Experimental Results Experimental Results Conclusions and Future Works Conclusions and Future Works

3. -3- Motivation Incremental static timing analysis (iSTA) is the backbone of post-layout design optimization Incremental static timing analysis (iSTA) is the backbone of post-layout design optimization –Using Signoff Timer –Using Internal Timer Gate Sizing/Vt-Swapping Post-Layout Signoff Post-Layout Optimizer Iterative invocation  Runtime increase TimingDiscrepancyTimingDiscrepancy iSTA Internal Timer iSTA Signoff Timer  Runtime increase  Less accuracy An accurate internal timer is needed STA Signoff Timer

4. -4- Motivation Challenges in matching signoff timer Challenges in matching signoff timer –Error propagation along paths –Error accumulation with netlist changes Error propagation on paths Error (internal timer – signoff timer) Error # logic depth along path # cell change Netlist change Error accumulation with netlist change Our goal: minimize the error Our goal: minimize the error

5. -5- Our Work We minimize divergence ‘d’ between internal and signoff timers We minimize divergence ‘d’ between internal and signoff timers Two basic techniques Two basic techniques –Learning-based modeling of wire delay and slew –Offset-based timing correlation We achieve small divergence ‘d’ runtime accuracy Signoff Timer d Internal Timer d Learning-based modeling Offset-based timing correlation

6. -6- Outline Motivation Motivation Learning-based Interconnect Modeling Learning-based Interconnect Modeling Correlation Methodology with Signoff Timer Correlation Methodology with Signoff Timer Experimental Results Experimental Results Conclusions and Future Works Conclusions and Future Works

7. -7- Preliminary: Delay and Slew Delay : 50% of input transition to 50% of output transition Delay : 50% of input transition to 50% of output transition Slew : 10% to 90% of transition Slew : 10% to 90% of transition Gate delay and slew: little divergence between timers Gate delay and slew: little divergence between timers –Lookup table-based method is used  not in our scope Wire delay and slew: challenging to match signoff timer Wire delay and slew: challenging to match signoff timer –Wire delay and slew models in signoff timer are unknown Delay Slew 50% 10%90%

8. -8- Error Distribution of Analytical Models Existing analytical models Existing analytical models Elmore (EM) [Elmore98] D2M [Alpert00] PERI [Kashyap02] Lognormal Slew (LnS) [Alpert03] Wire slew 80%  Regression  Regression EM/LnS: overestimate D2M/PERI: underestimate  Classification Hard cases cannot be estimated by any single model Hard cases Wire delay

9. -9- Why Classification? Data points in each class have stronger linear fit between measured and estimated values after classification Data points in each class have stronger linear fit between measured and estimated values after classification Estimated values Measured values

10. -10- Classification Our “alpha” is chosen empirically Our “alpha” is chosen empirically Alpha reflects degree of significance of ramp input on delay metric [Kashyap02] Alpha reflects degree of significance of ramp input on delay metric [Kashyap02] Model 1 Model 2 Model 1 Model 2 Model 3 Wire slew Wire delay

11. -11- Learning-based Interconnect Modeling Our methodology Our methodology –Classification + Least-Squares Regression (LSQR) Collect training data LSQR Classification

12. -12- Learning-based Interconnect Modeling Exhaustive search for the best regressor(s) and classifier(s) Exhaustive search for the best regressor(s) and classifier(s) –Increasing the number of regressors/classifiers improves the accuracy until a certain point The number of regressors The number of classifiers 0 1 2 1 23 20ps 23ps 21ps 15% -8% -30% 16ps 14ps -12% -33% 14ps 0% Maximum absolute wire delay error The number of regressors The number of classifiers 0 1 2 1 23 73ps 46.8ps 46.5ps -36% -0.0% -23% 36ps 33ps -8% -29% 31.5ps -4.5% -11% 32ps -1.5% Maximum absolute wire slew error Experimental results with all testcases (ISPD-2013)

13. -13- Learning-based Interconnect Modeling Learning-based models for wire delay and slew Learning-based models for wire delay and slew Wire delay modeling -1.722.350.96 -1.051.271.02 -2.721.412.50 Wire slew modeling -3.442.07 -2.391.59 -1.881.30

14. -14- Outline Motivation Motivation Learning-based Interconnect Modeling Learning-based Interconnect Modeling Correlation Methodology with Signoff Timer Correlation Methodology with Signoff Timer Experimental Results Experimental Results Conclusions and Future Works Conclusions and Future Works

15. -15- Static Timing Analysis Timing slack is calculated by STA Timing slack is calculated by STA Endpoint (primary output, input of FF) timing slack errors are reported for evaluation Endpoint (primary output, input of FF) timing slack errors are reported for evaluation Calculate slew Calculate delay Calculate AAT/RAT Calculate slack 3 4 5 6 11 12 15/15 /12 /11 /6 /5 /6 /5/2 /0 /2 AAT / RAT / slack = RAT - AAT / slack = RAT - AAT

16. -16- Correlation with Signoff Timer Use timing information from signoff timer to compensate the difference (error) between internal and signoff timer Use timing information from signoff timer to compensate the difference (error) between internal and signoff timer Previous work: [Moon10] Endpoint slack offset-based correlation Previous work: [Moon10] Endpoint slack offset-based correlation –Can match slack in critical paths –May not be accurate when critical paths change iSTA Signoff Timer iSTA Internal Timer Request timing information offset = signoff timer – internal timer

17. -17- Correlation with Signoff Timer Offset is calculated at each STA stage Offset is calculated at each STA stage Correlated timing (slew/delay/AAT/RAT/slack) = timing values from internal timer + offset Correlated timing (slew/delay/AAT/RAT/slack) = timing values from internal timer + offset Calculate slew Calculate delay Calculate AAT/RAT Calculate slack SlewSlewDelayDelayAAT/RATAAT/RATSlackSlack offset = signoff timer – internal timer Slew offset Delayoffset AAT/RAToffset Slackoffset Signoff timer Internal timer

18. -18- Correlation Method vs. Quality Maximum absolute endpoint slack error for each correlation method Maximum absolute endpoint slack error for each correlation method AAT/delay/AAT+slew/delay+slew correlations give 10X more accuracy during netlist changes compared to slack correlation [Moon10] AAT/delay/AAT+slew/delay+slew correlations give 10X more accuracy during netlist changes compared to slack correlation [Moon10] (ps) Experimental results with fft testcase (ISPD-2013) AAT, delay, AAT+slew, delay+slew correlation slack correlation 10X

19. -19- Timer in Post-Layout Optimizer Internal timer for a post-layout optimizer Internal timer for a post-layout optimizer Correlate() Netlist change iSTA() # cell change > N? Offset yes no invoke signoff timer

20. -20- Outline Motivation Motivation Learning-based Interconnect Modeling Learning-based Interconnect Modeling Correlation Methodology with Signoff Timer Correlation Methodology with Signoff Timer Experimental Results Experimental Results Conclusions and Future Works Conclusions and Future Works

21. -21- Experimental Environment Technology : Liberty from ISPD-2013 Gate Sizing Contest Technology : Liberty from ISPD-2013 Gate Sizing Contest Testcases : ISPD-2013 testcases Testcases : ISPD-2013 testcases Signoff tool : PrimeTime© F-2011.06-SP3-7 Signoff tool : PrimeTime© F-2011.06-SP3-7 Benchmark#cells#nets#PI#FFs#pins#PO pci_bridge323060330763160335987813201 fft3276633792102619841053551984 matrix_mult156440159642320228984599461600 edit_dist1266651292272562566137460612

22. -22- Error between Internal and Signoff Timer Maximum absolute endpoint slack error for all (delay, slew) pairs Maximum absolute endpoint slack error for all (delay, slew) pairs Correlation-based approach can improve accuracy Correlation-based approach can improve accuracy (delay: D2M, slew: ML) shows the best result (delay: D2M, slew: ML) shows the best result without correlation (ps) with correlation Testcase: fft (ISPD-2013) with correlation (ps) (delay: D2M, slew: ML) 10X

23. -23- Conclusions and Future Works Learning-based methodology can improve accuracy for endpoint timing slack estimation Learning-based methodology can improve accuracy for endpoint timing slack estimation AAT/delay/AAT+slew/delay+slew offset-based correlation methods can achieve 10X accuracy improvement for timing slack estimation AAT/delay/AAT+slew/delay+slew offset-based correlation methods can achieve 10X accuracy improvement for timing slack estimation Future works Future works –Enhance model robustness across different libraries and testcases –Minimize the overhead of correlation methodology with a given accuracy –Application: industry-strength gate sizing optimizers

24. Thank You!