1. FPGA Hardware Synthesis Jessica Baxter

2. Reference M. Haldar, A. Nayak, N. Shenoy, A. Choudhary and P. Banerjee, “FPGA Hardware Synthesis from MATLAB”, Fourteenth International Conference on VLSI Design, 2001 pp. 299 -304

3. Introduction Why use FPGAs? –Faster growth of transistor density –More complex designs allowed

4. Introduction Why use MATLAB? –More intuitive, easier to learn –Well defined set of library functions –No pointers or complex data structures –Popular program

5. Architecture WildChild –9 FPGAs –See literature for detailed description

6. Synthesis Flow

7. MATLAB AST MATLAB code is parsed based on a formal grammar

8. VHDL AST Created from MATLAB AST Optimizations take place Traversal of VHDL AST creates VHDL code VHDL is the hardware description language Allows memory pipelining

9. Scalarization of MATLAB AST MATLAB uses arrays VHDL uses elemental operations MATLAB has no sense of size or shape Must infer shape Matrix functions become loops

10. Scalarization of MATLAB AST A = B + C Scalarized For i=1:n For j=1:m A(i,j) = B(i,j) +C(i,j); end;

11. Levelization of MATLAB AST Only 3 operands per statement allowed Advantage: Different operations can be scheduled independently to save time Allows pipelining Resources can be reused

12. Levelization of MATLAB AST Unlevelized A[i + 1] = b + c Levelized t1 = b + c t2 = i + 1 a[t2] = t1

13. Handling Memory Accesses Only one memory access per statement Handled in levelization phase

14. Methods Benchmarks –Matrix multiplication –Edge Detection algorithm Important in image processing Run in two different environments –VHDL simulator –Manually designed hardware

15. Results VHDL simulator –Reduces design time –Enables more complex designs –Higher level of abstraction Manually designed hardware –Longer design time –Runs faster

16. Conclusion MATLAB to hardware description in VHDL to run on any FPGA Improve designs produced by compiler Reduce design time Runs 5X slower

17. Future Directions Pipelining Caching Memory Packing Precision Analysis Parallelizing Reduce run times so that it approaches run times of manually designed hardware