1. COE4OI5 Engineering Design Chapter 1: The 15 minutes design

2. Copyright S. Shirani 2 Simple design example An OR function with two inputs will be designed using Quartus II CAD tools. The design will be entered using schematic capture and VHDL The design will be simulated An FPGA on the UP3 board will be programmed to implement the OR.

3. Copyright S. Shirani 3 Design process for schematic or VHDL entry.

4. Copyright S. Shirani 4 Simple design example (UP3) The inputs to the OR gate will be two pushbuttons and the output will be displayed using an LED (all on the UP board no external wiring is required) Function: turn on the LED when one OR the other pushbutton is pushed. Pushbuttons PB1 and PB2 are connected to pins 62 and 48 (you can get this info from Table 2.4 of the book or the UP3 manual on the CD) The pushbuttons are “active low” (connect zero volt to the pins when they are pushed)

5. Copyright S. Shirani 5 Simple design example (UP3) UP3 has four LEDs To turn the LED on the board you should output a low signal.

6. Copyright S. Shirani 6

7. 7 Connections between the pushbuttons, the LEDs, and the Altera FLEX device.

8. Copyright S. Shirani 8 Equivalent circuits for ORing active low inputs and outputs. Since the pushbuttons generate inverted (active low) signals and LED requires inverted signal to turn on, we built an OR gate with inverted inputs and output.

9. Copyright S. Shirani 9 Figure 1.6 Creating a new Quartus II Project.

10. Copyright S. Shirani 10 Figure 1.7 Setting the FPGA Device Type.

11. Copyright S. Shirani 11 UP3 is available with two different sizes of Cyclone FPGAs: EP1C6Q240C8 and EP1C12Q240C8 The one in the lab is EP1C12Q240C8 For UP2 the FPGA is EPF10K70RC240-X For number X look at the FLEX chip on the board

12. Copyright S. Shirani 12 Figure 1.8 Creating the top-level project schematic design file.

13. Copyright S. Shirani 13 Figure 1.9 Selecting a new symbol with the Symbol Tool.

14. Copyright S. Shirani 14 Figure 1.10 Active low OR-gate schematic example with I/O pins connected.

15. Copyright S. Shirani 15 Table 1.1 Hardwired connections on the FPGA chips for the design. I/O Device UP 3 Pin Number Connections UP 1 & UP 2 Pin Number Connections PB1 62 (SW7) 28 (FLEX PB1) PB2 48 (SW4) 29 (FLEX PB2) LED 56 (D3) 14 (7Seg LED DEC. PT.)

16. Copyright S. Shirani 16 Figure 1.11 Assigning Pins with the Assignment Editor.

17. Copyright S. Shirani 17 Figure 1.12 Active low OR-gate timing simulation with time delays.

18. Copyright S. Shirani 18 Figure 1.13 ALTERA UP 3 board showing Pushbutton and LED locations used in design

19. Copyright S. Shirani 19 Figure 1.14 ALTERA UP 2 board with jumper settings and PB1, PB2, and LED locations

20. Copyright S. Shirani 20 Table 1.2 Jumper settings for downloading to the UP2 MAX and FLEX devices.

21. Copyright S. Shirani 21 Figure 1.16 VHDL Entity declaration text.

22. Copyright S. Shirani 22 Figure 1.17 VHDL OR-gate model (with syntax error).

23. Copyright S. Shirani 23 Figure 1.18 VHDL compilation with a syntax error.

24. Copyright S. Shirani 24 Figure 1.22 Timing analyzer showing input to output timing delays.

25. Copyright S. Shirani 25 Figure 1.23 Floorplan view showing internal FPGA placement of OR-gate in LE and I/O pins

26. Copyright S. Shirani 26 Figure 1.24 ORgate design symbol.