Our programmer needs to do this !

Our programmer needs to do this !
GRP Machine Details Memory Registers r11 r0 r1 r2 r3 r4 r10 ALU .. 8 16 24 32 Load from Memory Store to Memory Load reg from mem Add reg to reg into reg Store reg in mem Our programmer needs to do this ! We can generalise ths idea to design a realistic CPU. We have and ALU, which does the required function, such as “add”. We have a load of “registers” which feeds the CPU (and eats its output), and of course we need some memory (static or dynamic RAM chips elsewhere on the motherboard) which contain the numbers to be processed. A software application such as Excel” will load the numbers inserted by the user into this memory.

Programs are Numbers Let’s consider a spreadsheet cell which adds two numbers x + y. This cell and its instruction is in memory. 1. Application But it is REPRESENTED in different ways 4. Instructions in memory are just numbers 2. High Level Language 5. Memory stores these as bits w = x + y 16 24 32 We all know that DATA are just numbers which our programs add, subtract etc? But what are computer PROGRAMS? Well these are also just numbers! Wow, so both data and programs are NUMBERS. Everything we feed a CPU consists of NUMBERS. Let’s see how this works. (1) Here’s an Excel spreadsheet where the number in cell B3 is calculated by adding the numbers in cells B2 and C3. But Excel is written in a “High Level Language” (such as “C”) where an addition is “programmed” as a line of code w = x + y, (2). But our CPU cannot understand this line of code, it needs explicit instructions to get the values of “x” and “y” stored somewhere in memory, load these values into its electronic registers, add these numbers, then write them into another register. This is shown in (3) as the “assembler” instructions “load reg(ister) from mem(ory) followed by add reg(ister) to reg(ister (and place the result into another reg(ister). But again, these “assembler” instructions are written as text, for we mere human mortals to understand. The computer registers contain NUMBERS, so these “assembler” instructions are converted to numbers by the “assembler” software. So we have a list of encoded instructions, represented as numbers within memory (4). But these numbers must be converted to electronic signals to make the components of the CPU work. This is where BINARY encoding comes in. Any number, e.g. “43” can be encoded in binary, “ ” and each of these binary digits is “0” (off) or “1” (on). That’s the language of electronics. So this number can be converted into electronic signals which run along the “wires” of our CPU, to tell the ALU what to do, to select the registers to provide the data (numbers) for the required computation, (5) and (6). So there’s a hierarchy: From application interface, to high-level program, down to assembler and down to the electronic signals. The fundamental principle is that INSTRUCTIONS can be encoded as NUMBERS and a BINARY representation of the numbers is able to run the ELECTRONIC CIRCUITS of our computer. 3. Assembler Instructions 6. Onto the bus wires as signals load reg from mem add reg to reg into reg

Let’s take a RISC. What do we need ?
Let’s build a Computer Let’s take a RISC. What do we need ? Memory Registers ALU Control Circuits A programming language A good Name - Simple Although Meaningful So let’s begin our journey to build a Computer, well, an ALU. What do we need? (1) Memory to store our data (NUMBERS) and our program (NUMBERS). (2) Registers, to hold these numbers as we manipulate them to compute a calculation, such as (3 + (4 x 2)) .Then we need (3) an ALU to do the “add” and “multiply” operations. We must be aware of the CONTROL path, signals (4) which tell the various CPU elements what to do (e.g. to tell the ALU to “add” and not to “subtract”). There must be a “LANGUAGE” (5) which is written by a human but which can be converted to NUMBERS understood by the CPU. And, of course, we need a sexy name for our CPU, since we intend to sell it and become rich!. Intel have chosen “Pentium” and “Itanium”, I’ve chosen “SAM”. We’ll see who makes most bucks!.

What’s needed to build Sam-4 ?
Arithmetic – Logic Unit to do the maths business Data memory to hold source and results of our work PC Code Memory Registers to hold results of computations X Y W r1 r2 r0 1 7 mar mdr Data Memory I developed “SAM-4” for this advanced class. Here are some of its structural elements which are reflected in the design of many commercial microprocessors. There is the ALU which does the computations (add, subtract, etc.). There is the REGISTER FILE which holds intermediate results of computations. We also need two blocks of memory or “cache” on the CPU chip. One is the “data memory” containing the data we must access, and the other is the “code memory” containing the machine-code representation of the operations we wish to perform on the data. These on chip memory caches are of course connected to the main system memory or RAM located on the motherboard. Code Memory – to store the program

Program Memory PC = 4 12 8 4 Code Memory add halt store load Data out
Code Memory add halt store load Data out Memory stores program instructions at a sequence of byte addresses. Each instruction is 32 bits, so the addresses increment by 4 bytes. Here the Program Counter input address 4 to the memory which reads out the data word (32 bits) at address 4. This is the instruction ‘add’ Program memory consists of a sequence of locations where the machine instructions are stored. Note that the addresses of the memory cells go up in jumps of 4 Bytes. This is because each machine instruction takes 4 x 8 = 32 bits of space for storage. The instruction being read out of program memory is specified by the “Program Counter” (PC) which is a 32-bit register. Address in

Registers, Registers 1. Registers Store data at addresses. Yep, that’s Memory ! 2. There are TWO read ports (X and Y) where data can be simultaneously read out of the reg file. X Y W r1 r2 r0 4. The addresses for the read ports (X and Y) and the write port (W) come in here. 3. Multiport Registers have an input port (W) where data is send to be written into the register file. Registers are found in the CPU and are basically super-fast memory cells. Note the REGISTER FILE has two outputs “X” and “Y”, since computations (such as X+Y) need two elements of data. The data-paths are shown in red in the diagram. It’s along these paths (electronic wires) that the data “X” and “Y” travel. But what about the blue “X” and “Y”. Well, these are CONTROL signals; they indicate which register must be accessed at any point in the computation, For example, if data “3” is stored in register r1 and data “4” is stored in register r6, then if our program wishes to add these numbers, we must tell the ALU to get its input from r1 and r6. The ALU will perform the requested addition and will have the result. This result “W” will be written into a register. The DATA path is the red “W”, containing the number provided by the ALU. The blue “W” indicates into which register this result must be deposited. An “address” into the REGISTER FILE.

Data Memory The Memory Data Register (MDR) is a parking place for data coming and going from the memory. Here’s the memory 1 7 mar mdr The Memory Address Register holds the address of the data location selected for read or write e,g, 7 Let’s now consider the data memory. This is simply a load of super-fast memory cells, situated on the CPU containing the data numbers we wish to process. Each cell contains a number. And each cell has an “address” which indicates the cell containing a particular number. So we need two additional registers associated with this data memory. One the “memory access register” (MAR) holds the number which is an address pointing to the memory cell which we need to read from or write to at any time. If we are to compute (3 + 1), then the MAR tells us where the “3” and the “1” are stored, and also where th write the result “4”. Both registers and all memory cells are to be 32-bits wide. 7

Here’s Sam Code Memory Data Memory ALU Instruction reg r1 r2 r0 X Y W
1 7 mar mdr Finally, here’s the components discussed so far assembled into a complete CPU. Remember wires joining blue inputs represent elements of the CONTROL path while those joining red inputs are elements of the DATA path. The nature of other wires will become clear. There are three additional elements introduced above. First two wedge-shaped objects, these are “multiplexers” (mux) which is an electronic-eng term for “switches”. They have two inputs and one output. Which input is allowed through the mux is selected by a control signal. And finally there’s the “instruction register” which receives the machine instruction from code memory, and converts it to 32 data and control signals.

The Instruction Register
Loaded with the instruction, the IR decodes this into bits which drive the CPU digital logic circuits Code Memory add Add r2,r1,r3 add 2 1 3 010110 00010 00001 00011 unused So what happens to these binary numbers? Well the IR emits them as electrical signals, one wire for each binary bit. The first six bits “010110” are sent to the ALU and tell it to ADD. The next 5 bits “0010” are sent to the register file to select r2 during the register-write stage. The next 5 bits “0001” and the five bits after that “0011” are sent to the register file during the register read stage, to select the required registers to read, and send their data into the ALU. This is pure magic. And it’s quite surreal, since, think a bit, the elements of the program instruction “add r2,r1,r3” are converted to NUMBERS (just like DATA) and then into electrical signals. Electronic Wires

Instruction Encoding Example
destination All Sam’s instructions take up 32 bits. opcode Source regs add rd rs rt unused Sam’s instructions start with the opcode then the destination register then the source register rd <- rs + rt e.g. add r3, r1, r2 means r3 = r1 + r2 First 6 bits for the opcode. The assembler programmer writes a line of code such as “add r2,r0,r1” as we have seen. When this enters the IR, it’s not this text, but it’s a load of BITS. These bits must do the following functions: (1) tell the ALU to “add”, (2) select r0 and r1 as source registers to be read, (3) select r2 as the destination register where the result is to be written. These registers are identified by the numbers 0,1 and 2 respectively, so its THESE numbers which are located (in binary format) in the IR. This is shown here, where the 32 bits of the instruction stored in the register are comprised of first 6 bits used to identify the ALU operation (add, sub, mult, div), followed by 5 bits indicating the destination register rd, followed by 5 bits indicating the first source register rs, followed by 5 more bits identifying the second source register rt. The remaining 11 bits are unused here. 010110 00011 00010 00001 unused 3 2 1 Nr of Bits 6 5 5 5 11

Fetch-Execute Cycle 1. Fetch instruction from memory
5. Write back results to registers add r3,r2,r1 r3 <- ALU 4. Do any Memory Access 2. Decode the opcode and read any registers None needed SAM-4 works using a 5-stage fetch execute cycle. Irrespective of the particular machine instruction being executed at any time, the actual operation carriend out at each of the 5 stages is the same. So in Stage 1, the instruction is fetched from memory and loaded into the instruction register. In Stage 2 the instruction is DECODED, ie turned into raw electrical signals on wires, and also any register read operations are performed. This example adds the contents of r1 and r2 and puts the result into r3. So we need to read the contents of r1 and r2 at this point. In Stage 3 any ALU operations are performed, so we must actually do the addition. Stage 4 is only used for memory accesses. Since this is neither a load or store instruction, there is no memory access, so nothing happens here. Fingally Stage 5 is the time when any WRITES to registers are performed. Since the instruction specifies that we must write to r3, that’s what we do here. ALU <- r1 ALU <- r2 3. Do any ALU operations ALU add Get contents of address 1

Example ld r0 , [1] ld r1 , [2] add r2,r1,r0 st r2 , [7]
Load r0 with data at address 1 Load r1 with data at address 2 Add r0 and r1. Put result in r2 Store r2 in memory address 7 Note each of these instructions runs through 5 steps of its own F-E Cycle

1. Instruction Fetch Ld 0 1 Ld r0,[1] Code Memory Data Memory ALU X Y
Ld r0,[1] X r0 1 Y r1 Code Memory r2 mdr W Data Memory ALU Stage 1: Fetch the instruction into the instruction register. Note where the address “1” appears next to the horizontal wire on the right, and the register identification number “0” which comes out of the left-most wire at the bottom. PC = 0 mar 7

2. Decode, Reg Ops + Ld 0 1 Ld r0,[1] Code Memory Data Memory ALU X Y
Ld r0,[1] X r0 1 Y 1 r1 Code Memory r2 mdr W Data Memory ALU Stage 2: decode, The instruction is converted to electronic signals inside the IR. At this stage, one signal is emitted, the memory address. It proceeds through the MUX into the ALU. Why, well it’s got to find its way to the MAR and there’s a path from the IR to the MAR via the ALU. PC = 4 mar 7 +

3. ALU Operation Ld 0 1 Ld r0,[1] Code Memory Data Memory ALU X Y X r0
Ld r0,[1] X r0 1 Y 1 r1 Code Memory r2 1 mdr W Data Memory ALU Stage 3: There’s no ALU function to execute, but the address passes through the ALU and thence into the MAR where it is stored ready to address the correct data memory cell 1 PC = 4 mar 7

4. Memory Access Ld 0 1 Ld r0,[1] Code Memory Data Memory ALU X Y X r0
Ld r0,[1] X r0 1 1 Y r1 Code Memory r2 mdr W Data Memory ALU Stage 4: Here any memory access is to be performed. The address of the cell “1” we must write from is already in the MDR, so here we can read out the value stored there and read it into the MDR. 1 PC = 4 mar 7 7

5. Register Write Ld 0 1 Ld r0,[1] Code Memory Data Memory ALU X Y X
Ld r0,[1] X r0 1 Y r1 Code Memory r2 mdr W Data Memory ALU Stage 5: Register write. The results of the memory access must be written into the correct register, specified by the machine instruction. This is r0 in this example. Two things happen here: (1) The data, stored in the MDR on the previous stage is read out and fed into the REGISTER FILE input port “W”. (2) The correct register to receive this data must be iniducated to the register file. This register is specified in the machine instruction, here “0”. So that number is output from the IR and fed into the blue “W” input which selects the appropriate register, r”0”. PC = 4 mar W 7

1. Instruction Fetch Code Memory Data Memory ALU add 2 0 1 X Y X
X add r2,r0,r1 r0 1 Y r1 Code Memory r2 mdr W Data Memory ALU Let’s take a second example of an addition instruction. Stage 1: Instruction fetch, gets the instruction into the ALU. That’s all. PC = 4 mar 7 W

2. Decode, Reg Ops + Code Memory Data Memory ALU add 2 0 1 X Y X
X add r2,r0,r1 r0 1 Y r1 Code Memory r2 mdr W Data Memory ALU Stage 2: The add instruction has been written to add the contents of r0 and r1 and put the result into r2. So here we must read the contents of r0 and r1 into the ALU. So the IR emits two control signals, these are the addresses of the registers we need to read from in the register file. So “x=0” and “Y=1”. As soon as these signals are sent to the register file, this file responds by sending the numbers contained in the selected registers to the ALU. Note that “Y” passes through the multiplexer. (In the previous example, the multiplexer selected the address “1”, now it switches to select the output “Y” of the register file. So far, so good. PC = 8 mar 7 W +

3. ALU Operation Code Memory Data Memory ALU add 2 0 1 X Y X
X add r2,r0,r1 r0 1 Y r1 Code Memory r2 mdr W Data Memory ALU Stage 3: This is the stage where the ALU does its stuff. The output is immediately broadcast to the output bus, where it’s ready for any component which must receive it during the next stage. PC = 8 mar 7 W

4. Memory Access Code Memory Data Memory ALU add 2 0 1 X Y X
X add r2,r0,r1 r0 1 Y r1 Code Memory r2 mdr W Data Memory ALU Stage 4: Memory access. The add instruction does not access memory, so nothing happens here. PC = 8 mar 7 W

5. Register Write Code Memory Data Memory ALU add 2 0 1 X Y X
X add r2,r0,r1 r0 1 Y r1 Code Memory r2 mdr W Data Memory ALU Stage 5: Register write. Here the ALU output, the requested sum is input into the register file, via the red “W” input port. Of course the register file needs to know which register to write this result into. So the IR outputs the programmed destination register, here r2. This number is sent from the IR to the register file’s blue “W” input. PC = 8 mar 7 W

Control Path 001010 00010 00001 00011 unused add r2, r1, r3 The add instruction is decoded and produces digital signals which select the + function in the ALU ALU r1 r3 - + Add ! sub r2, r1, r3 000101 00010 00001 00011 unused ALU The sub function decoded produces different digital signals r1 r3 Let’s dwell a little more on the “control path”, how the electrical signals emitted by the first 6 bits, corresponding to the programmed operation, actually tell the ALU which operation to perform. Well, let’s say the ALu has two control input signals. One, “+” when asserted makes the ALU do an add, the other “-”, when asserted makes the ALU subtract. So in this example, the “add” operation is represented by the binary number “001010”. Trace the “1”’s in this number. They pass through an AND-gate, so if they are both high the gate will output a high. This is connected to the “+” control input of the ALU, so the ALU does an addition. When a “sub” instruction is encountered, encoded as binary “000101” then the “1”’s are combined in the other AND-gate, and when both asserted output a “1” to the “-” input of the ALU, which responds by subtracting. So each machine instruction (add, subtract, mult, div) is encoded as a particular pattern of bits which drive wires through digital logic to select the requested ALU function. Clever eh? (But not that hard to understand!). - + Subtract !

Sam and MIPS are 32 bit 32 bits wide add rd,rs,rt ldr rd,[rs+c]
001010 00110 01001 00011 unused opcode rd rs rt unused ldr rd,[rs+c] 001010 00010 00001 opcode rd rs 16-bit address 001010 ldr rd,[c] There are many instructions in a RISC microprocessor. We shall look at some of these shortly. But there’s one key element. All instructions fit into 32 bits. This makes the construction of the electronics easier than if instructions required a different number of bits. Intel’s “x86” architecture is not like this – it uses a variable number of bits, and has made the design of the x86 CPUs much more tricky than the SPARC or MIPS processors. But that’s another story (which I will tell you if you like).. Here’s three examples of how the 32 bits available may be used in different ways. The top is the example we have already seen. The centre load-register example calculates the source memory location as a SUM of the contents of rs and a constant c, where c is a 16-bit number. The bottom load-register example uses a 26-bit constant address to define the source of the data to be loaded. This could be an important number such as a conversion factor from kilometers to miles, centigrade to farenheit, ie something which does not change. opcode 26-bit address

Other Arithmetic Instructions
destination rd <- rs - rt opcode Source regs sub rd rs rt unused 6 5 Nr of Bits Same coding applies to other arithmetic instructions sub r3,r2,r1 and r2,r1,r0 or r5,r1,r2 Nothing much here. This is just like the add, except that the first 6 bits which define the operation will\ be different.

A simple ‘Load’ instruction
destination ‘Load into rd the contents of memory at address which is in reg rs.’ Simple! opcode Single source reg ld rd rs unused memory 2. Load the data into r9 ldr r9 , [r1] 1 2 3 1. Let’s say have already loaded r1 with 3 3 145 145 r9 4 115 Here’s your first example of a load instruction. Here we load the contents of the memory cell, whose address is given by the contents of r1. Then we put the result into r9. So let’s say be have put “3” into “r1), then this instruction accesses memory cell “3” which contains “145” and then writes this result into register “r9” in the register file. 2. Get data from mem at addr r1 (=3) 5 231 6 69 7 145

The mem address is formed as a sum
A more complex ‘Load’ Load register rd with the contents of memory which you find at address r1 + c. destination opcode Source ldr rd rs constant c 7 69 6 231 5 115 4 145 3 2 1 memory ldr r9 , [r ] 231 r9 The mem address is formed as a sum A more complex register-load. The destination register is the same as in the previous example, “r9”. But the source address is contained in the bra-kets “[R1+2]”. This means that we must first read out the contents of register r2 (that’s “3”) and add this to the constant “2”, which gives us “5”. This “5” is sent to the MAR which will access cell “5” and return to us the number stored there, which is “231”. 5 231

… and a ‘Store’ instruction
Source What’s this? destination opcode Note here the data is moved from destination to store. Confusing? Mm. str rd rs constant c 7 69 6 196 5 115 4 145 3 2 1 1. Get data from r1 str r9 , [ r ] 196 r9 Rather like the previous load, this instruction stores the contents of r9 into the memory cell whose address is the “contents of r1 plus”. The reversal of “source” and “destination” fields may be a bit confusing. But it makes good sense to the electronic engineers who actually produce the chip! 5 2. Write it to memory 196

All reference to memory has gone!
‘Load Immediate’ destination opcode In load immediate we get the constant C immediately following the opcode into the reg. ldi rd Constant C All reference to memory has gone! ldi r9 , 5 5 r9 “Immediate” instructions load the number, or constant “C” which IMMEDIATELY follows, into the specified register. So “ldi r9,5” will stick 5 into r9. Note the different op-code “ldi” rather than “ldr”. 5 Load ‘5’ straight into r9

A Summary So Far … Example add r3,r1,r1 add rd,rs,rt str r6,[r1 + 1] str rd, [rs + c] str r0, [r1] st rd, [rs] ldr r2,[r3 + 4] ldr rd, [rs + c] ldr r2,[4] ld rd, [rs] ldi r0,3 ldi rd,C Now it’s time to move on and look in detail at the hierarchy of computer languages – to see the influence on the ISA. Let’s consider the examples: (1) load register r0 with the immediately following number “3”. So after this r0 will contain 3. (2) Load the register r2 with the contents of data memory at constant address 4. (3) Load register r2 with the data stored in memory location which is calculated as the “sum of the number in r3 and the constant 4”. (4) Store the number contained in register r0 into the memory cell whose address is contained in register r1. (5) Store the number, into register r6, which is located in the memory cell whose address is the “sum of the number in r1 and 1”. (6) Add the contents of the register r1 with the contents of the register r1 and put the result into r3. What’s this? Clearly we are doing “ x + x” which gives us “2x”. So we are multiplying by 2!

Assembling a Spreadsheet
Excel Application The Great Idea here is that the ISA we need at the bottom must serve the grand master at the top, the Application. Main() { int f,g,h; f = g + h; } ld r0, [ g ] ld r1, [ h ] add r2,r0,r1 st r2, [ f ] HLL Imple-mentation The ISA must support the HLL implementation When we use an application, like Excel, say to add two numbers, in this example contained in cells B2 and C3, and write the result into cell B3, then our intention must be executed by the electronic signals in our CPU. So how do we get from the human desire to the operations executed by the CPU? Here’s a suggestion: Programs like Excel are written in a high-level language (such as “C”) which when compiles produces assembler instructions which can be digested by the CPU and emitted as electronic signals to make the circuits on the CPU work to provide the top-level request of the Excel application. Fine. So what? Well, there are two reflective approaches to this hierarchy: (1) Either we must work “top-down” and, from a knowledge of the “Excel”-level processing we wish to achieve, we design the low-level machine, the CPU. Else (2) we must work “bottom-up”, and discover, given a particular digital electronic design, which “Excel”-level operations are possible. I leave it to you to decide which is the best approach! Electronics ISA Assembler

Arrays (= Tables) How do we sum the array of numbers in column B? 1. We would use the instruction ld r1,[r0 + B] where B=3, the start address of the array 2. Then we load r0 with 0 then 1, then 2, … to scan down the array One extremely important function in “Excel” (and most other applications) is to work with a SERIES of data elements. This may be a column of numbers in a worksheet, a list of names within a database. In computer memory, such series of data elements will be stored, starting at a particular memory location, lets say 301, and running on to another location or address, say 306 (I guess that’s 50 numbers). Ld r0 , 0 Ld r3 , 0 Ld r1, [r0 + 3] r0 (=0) +3 = 3

Get next cell, lad its value and add it to the sum, in r3
Arrays (= Tables) How do we sum the array of numbers in column B? Increment r1 to get the next data value inc r1 (0 + 1 = 1) ld r2,[r0 + B] where B=3, the start address of the array but now r- contains 0 One extremely important function in “Excel” (and most other applications) is to work with a SERIES of data elements. This may be a column of numbers in a worksheet, a list of names within a database. In computer memory, such series of data elements will be stored, starting at a particular memory location, lets say 301, and running on to another location or address, say 306 (I guess that’s 50 numbers). Inc r0 Ld r1, [r0 + 3] add r3,r3,r1 Get next cell, lad its value and add it to the sum, in r3

Making Decisions What about SAM? First load the test number 10
Let’s say we want to add 2 to a number B if another number C is equal to 10 You mean, ‘If C = 10, then add 2 to B’ First load the test number 10 … addi r3,r3,2 bne r2,r1,36 ldi r1,10 36 32 28 24 20 16 Yep Here’s how we would do it in C Branch around the add if(c == 10) b = b + 2; Branch if not equal r1 r2 to addr 36

Loops Let’s say we want to make the sequence 0,3,6,9,12 and stop.
We take 4 steps and each step add 3 x = x + 3 And a register to hold the sum at each step ldi r2 , 0 ldi r1 , 4 ldi r0 , 0 8 4 bne r0,r1,12 addi r0 , r0 , 1 addi r2 , r2 , 3 20 16 12 So we need a register to keep track of the number of steps (r0) 1 2 3 4 3 6 9 12 Branch unless r0 = r1 = 4 r0 r2

Accumulator Architecure
Get 3 from Memory and ADD ! 1. Assume 8 is already in the accumulator. The programmer writes .. 8 16 24 32 4 2 3 Accumulator 8 Add 3 3 8 ALU 2. The ALU does = 11 and writes the result back into the accumulator There are several “architectures” which can be used to produce useful CPUs. The “Accumulator” architecture was used in the early days of computing, it is simplistic and may not be representative of modern CPU technology. But you should know what it means! The basic idea is that a complex calculation (such as (3 + (4 x 2)) can be decomposed into a number of steps, and that the result of each step can be “accumulated” in one place, a register called, surprise, the “accumulator, So in the example (3 + (4 x 2)) which means, “first multiply 4 and 2, and then add 3 to the result”, first we send the “4” and the “2” (DATA) to the accumulator and supply a control signal MULTIPLY. These numbers. The result appears in the accumulator. Then we send the DATA “3” and the control signal ADD to do the addition. The slide here shows the second part of the computation: (4 x 2) = 8 has been computed and is already in the accumulator. So now we add the “3”. After this computation, the accumulator will contain “11”. Memory

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