1. PowerMixer IP : IP-Level Power Modeling for Processors Shan-Chien Fang 1 Jia-Lu Liao 2 Chen-Wei Hsu 2 Chia-Chien Weng 2 Shi-Yu Huang 2 Wen-Tsan Hsieh 3 Jen-Chieh Yeh 3 1 TinnoTek Inc, Taiwan (service@tinnotek.com.tw) 2 Dept. of Electrical Engineering, National Tsing Hua University, Taiwan 3 Industrial Technology Research Institute, Taiwan

2. Introduction Power dissipation has become a major design metric IR drop, signal integrity power budgeting, power tradeoff, battery lifetime power grid design, thermal analysis, packaging High-level power estimation enable power optimization in early stage achieve higher power saving fast but often suffer from inadequate accuracy PowerMixer IP IP-based power modeling/analysis tool bottom-up power modeling/analysis methodology fast and accurate power analysis for large SoC designs

3. Power Modeling Strategies Processor Model General IP Model PowerMixer IP 1.For general IP 2.Adopt operation-mode-based model 3.By observing user-defined operation mode and key signals 1.For general IP 2.Adopt operation-mode-based model 3.By observing user-defined operation mode and key signals 1.Specific for processor 2.Adopt instruction-level or stage-accurate model 3.By observing the program counter register and the instruction registers 1.Specific for processor 2.Adopt instruction-level or stage-accurate model 3.By observing the program counter register and the instruction registers

4. IP-Based Power Simulation μProcessor (3) Essential VCD (1) SoC Netlist(2) IP Power Models (.PMF) CacheBusDMAASICs …… (4) Std. Cell Power Library (4) Std. Cell Power Library PowerMixer IP (IP-Based Power Simulation) PowerMixer IP (IP-Based Power Simulation) Power Profile PowerMixer IP can significantly speed up the simulation process!

5. Processor Modeling Example: PAC-DSP Core Architecture  PACDSP core is a VLIW processor with 8 pipeline stages and 5 issues  ISA supports 206 instructions

6. Energy Model Complexity  Enumerate all possible instruction combinations 206 is total number of instruction 5 is number of instructions per issue O(206 5 )  Divide all instructions into instruction classes instructions with similar behaviors in one class divide instructions into 13 types O(206 5 )  O(13 5 )  Sum up the individual power of each instruction in a issue O(13 5 )  O(13)  Consider power consumption of an instruction in eight different stages O(13)  O(13*8) = O(104)

7. Divide the execution time of training programs into a number of basic periods Basic period the time period during which the program counter’s value is not changed calculate energy E i of each basic period i Basic Period of Processor Energy Model CLK PC 1000003910000040100000471000004e10000056 E1E1 E2E2 E3E3 E4E4 E5E5

8. Generate Energy Matrix Energy Equation for Each Basic Period Energy Matrix E i : energy consumption of the basic period i N i,s : number of times the s -th stage is executed in basic period i J s : one-time execution energy of the stage s s : pipeline stage id in each instruction class Solve the energy matrix to obtain J vector N i,1 x J 1 + N i,2 x J 2 + …… + N i,104 x J 104 = E i

9. Experimental Results Accuracy and Runtime Comparisons of IP-level Power Analysis General IP model Gate-level CLK STATUS ENDE AES Power Waveform IP DesignGate Count Accuracy ComparisonRun Time Comparison Gate-levelIP-levelErrorGate-levelIP-level Speedup AES88K63.20 mW63.29 mW0.14%120.1 sec0.37 sec324 X PACDSP248K18.9 mW18.3 mW-3.1%937.0sec2 sec 468 X AndesCore490K215.9 mW220.2 mW1.9%10133.3 sec32.21sec314 X 805125K1.53 mW1.54 mW0.7%316.7sec6.02sec52 X

10. Power Exploration & Design Trade-Off Application: H.264 (100K instructions) Specification: PAC-DSP with various caches @ 240MHz T Target : Execution time of different cache sizes T reference : Execution time of 32K cache size E Target : Energy of different cache sizes E reference : Energy of 32K cache size

11. Summary PowerMixer IP : IP-based power analysis tool Construct the power models of processors and other various IPs automatically Explore potential power-performance trade-offs at an early SoC design stage ~100X power simulation speedup with high estimation accuracy